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EECS 303 Lecture 1 1
Lecture 1
Introduction to Digital Logic Design
Hai Zhou
EECS 303Advanced Digital Design
Fall 2011
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EECS 303 Lecture 1 2
Outline
Class administration
Digital design methodology
Representations of Digital Design
Introduction to Mentor Graphics tools
READING:
Chapter 1
Chapter 2
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EECS 303 Lecture 1 3
Class Administration
Lectures twice a week, Tuesday-Thursday 3:30-
4:50PM
Instructor:
Hai Zhou
Office: L461 Tech EMAIL: haizhou@northwestern.edu
PHONE: 491-4155
Teaching Assistant
Peng Kang
Office: M314 Tech
EMAIL: pengkang2011@u.northwestern.edu
Web Page:www.eecs.northestern.edu/~haizhou/303/
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EECS 303 Lecture 1 4
Class Prerequisites
EECS 203: Introduction to Computer Engineering
Need to have basic understanding of digital systems,
logic gates, combinational and sequential logic
Need to have been exposed to UNIX since we will
use the Mentor Graphics tools on SUN
workstations
Class will form a background for other classes in
Computer Engineering
EECS 357: Introduction to VLSI CAD
EECS 355: ASIC & FPGA Design
EECS 361: Computer Architecture
EECS 391: Introduction to VLSI Design
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EECS 303 Lecture 1 5
Class Administration
Required Textbooks:
Mano and Kime, Logic & Computer Design
Fundamentals, Prentice Hall.
Classnotes
Copies of lecture transparencies to be made available
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EECS 303 Lecture 1 6
Class Grades
5 Homeworks
25% of grade
5 Labs
25% of grade
Midterm exam 20% of grade
Final exam
30% of grade
Homeworks and labs will be due at the beginning
of class on the due date
A penalty of 10% per working day will be assigned to
late assignments or labs
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EECS 303 Lecture 1 7
Lab Work
You will be introduced to the use of a commercial
computer aided design tool from Mentor Graphics
Will use the Sun workstations in the Wilkinson
Lab (3rd floor M wing of Tech)
Lab Hours: Open There will be 5 labs
Lab 1: Tutorial on Mentor Graphics (simple logic)
Lab 2: Design of combinational logic (8-bit adder)
Lab 3: Design of ALU and shifter
Lab 4: Design of a simple 8-state finites state machine
Lab 5: Use of VHDL for combinational and sequential
design
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EECS 303 Lecture 1 8
The Process of Design
Design
Initial concept: what is the function performed by the object?Constraints: How fast? How much area? How much cost?Refine abstract functional blocks into more concrete realizations
Implementat ion
Assemble primitives into more complex building blocksComposition via wiringChoose among alternatives to improve the design
Debug
Faulty systems: design flaws, composition flaws, component flawsDesign to make debugging easier
Hypothesis formation and troubleshooting skills
Implementation
Design
Debug
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EECS 303 Lecture 1 9
Digital SystemsDigital vs. Analog Waveforms
Analog:values vary over a broad rangecontinuously
Digital:only assumes discrete values
+5
V
5
Time
+5
V
5
1 0 1
Time
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EECS 303 Lecture 1 10
Digital Hardware Systems
Algebra: variables, values, operations
In Boolean algebra, the values are the symbols 0 and 1If a logic statement is false, it has value 0
If a logic statement is true, it has value 1
Operations: AND, OR, NOT
Boo lean Algebra and Log ical Operators
00
11
X Y X AND Y
01
01
00
01
X Y X OR Y
00
11
01
01
01
11
X NOT X
01
10
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EECS 303 Lecture 1 11
Digital Hardware Systems
Comb inat ional logicno feedback among inputs and outputsoutputs are a pure function of the inputs
e.g., full adder circuit:(A, B, Carry In) mapped into (Sum, Carry Out)
Network implemented fromswitching elements or logicgates. The presence of feedbackdistinguishes between sequent ialand combinat ional networks.
Comb inat ional vs. Sequent ia l Logic
-
--
X1X2
Xn
SwitchingNetwork
Z 1Z 2
Z m
-
--
ABCin
FullAdder
SumCout
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EECS 303 Lecture 1 12
Digital Hardware SystemsSequent ial logic
inputs and outputs overlapoutputs depend on inputs andthe entire history of execution!
network typically has only a limited number of unique configurationsthese are called statese.g., traffic light controller sequences infinitely through four states
new component in sequential logic networks:storage elements to remember the current state
output and new state is a function of the inputs and the old statei.e., the fed back inputs are the state!
Synchronous systemsperiod reference signal, the clock, causes the storage elements to
accept new values and to change state
Asynchrono us systems
no single indication of when to change state
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B3 B2 B1 B0 Val
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 81 0 0 1 9
L1
L
6L2
L3
L
7
L
4
L
5
Case Study of a Simple Logic Design:
Seven Segment Display Chip to drive digital display
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B3 B2 B1 B0 Val L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 1 1 0 1 1
L1
L
6
L2
L3
L
7
L
4
L
5
Case Study (cont.)
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Case Study (cont.)
Implement L4:
B3 B2 B1 B0 L4
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1 Some gate level implementation
of the Boolean function for L4
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EECS 303 Lecture 1 16
Representations of Digital Design:
SwitchesA switch connects two points under control signal.
when the control signal is 0 (false), the switch is open
when it is 1 (true), the switch is closed
when control is 1 (true), switch is open
when control is 0 (false), switch is closed
Normally Closed
Normally Open
Open
Switch
Control
Normally OpenSwitch
ClosedSwitch
True
False
OpenSwitch
Control
Normally ClosedSwitch
Closed
Switch
True
False
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EECS 303 Lecture 1 17
Switch RepresentationsExamples: routing inputs to outputs through a maze
Floating nodes:what happens if the car is not running?outputs are floating rather than forced to be false
Under all possible control signal settings
(1) all outputs must be connected to some input through a path(2) no output is connected to more than one input through any path
EXAMPLE:
IFcar in driv ewayOR(car in garageAND NOTgarage doorclosed)AND car runningTHENcan back out car
Car ingarage
Carrunning
True
True
Car can
back out
Garage doorclosed
Car in
driveway
EXAMPLE:
IF car in garageAND garage door openAND car runningTHEN back out car
TrueCar canback out
Garagedoor open CarrunningCar ingarage
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EECS 303 Lecture 1 18
Switch Representations
Imp lementat ion of AND and OR Func t ions w ith Switches
A
False
True
output
B A
False
True
output
B
AND functionSeries connection to TRUE
OR functionParallel connection to TRUE
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EECS 303 Lecture 1 19
Representations of a Digital Design
Truth Tablestabulate all possible input combinations and their associated
output values
Example: half adderadds two binary digits
to form Sum and Carry
Example: full adderadds two binary digits and
Carry in to form Sum andCarry Out
NOTE: 1 plus 1 is 0 with acarry of 1 in binary
A B
001
1
010
1
Sum Carry
011
0
000
1
A000
01111
B001
10011
Cin010
10101
Sum011
01001
Cout000
10111
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EECS 303 Lecture 1 20
Representations of Digital Design:
Boolean Algebra
NOT X is written as XX AND Y is written as X & Y, or sometimes X YX OR Y is written as X + Y
values: 0, 1
variables: A, B, C, . . ., X, Y, Zoperations: NOT, AND, OR, . . .
A
0011
B
0101
Sum
0110
Carry
0001
Sum = A B + A B
Carry = A B
OR'd together producttermsfor each truth tablerow where the function is 1
if input variable is 0, it appears incomplemented form;
if 1, it appears uncomplemented
Der iv ing B oolean equat ions from truth tables:
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EECS 303 Lecture 1 21
Representations of a Digital
Design: Boolean Algebra
A
0000111
1
B
0011001
1
Cin
0101010
1
Sum
0110100
1
Cout
0001011
1
Ano ther examp le:
Sum = A B Cin + A B Cin + A B Cin + A B Cin
Cout = A B Cin + A B Cin + A B Cin + A B Cin
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EECS 303 Lecture 1 22
Gate Representations of a Digital Designmost widely used primitive building block in digital system design
Standard
Lo gic GateRepresentat ion
Half Adder Schematic
Netl ist:tabulation of gate inputs & outputsand the nets they are connected to
Net:electrically connected collection of wires
Inverter
AND
OR
Net 1
Net 2
A
B
CARRY
SUM
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EECS 303 Lecture 1 23
Representations of a Digital Design:
GatesFul l Adder Schematic
Fan-in: number of inputs to a gateFan-out: number of gate inputs an output is connected to
Technology "Rules of Composition" place limits on fan-in/fan-out
Cin B A\Cin \ B \ A
A
B
CinSUM
Cout
A
B
B
Cin
A
Cin
Cout
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EECS 303 Lecture 1 24
Waveform Representationdynamic behavior of a circuitreal circuits have non-zero delays
Tim ing Diagram o f the Half Adder
sumpropagation
delay
circu it hazard:1 plus 0 is 1, not 0!
sumpropagation
delay
Output changes are delayed from input changes
The propagation delay is sensitive to paths in the circuit
Outputs may temporarily change from the correct value to thewrong value back again to the correct value: this is calleda gl i tchor hazard
100 200
A
B
SUM
CARR Y
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EECS 303 Lecture 1 25
Block Representation of a Digital Designstructural organization of the design
black boxes with input and output connections
corresponds to well defined functions
concentrates on how the components are composed by wiring
Full Adder realized in terms ofcomposition of half adder blocks
Block diagram representationof the Full Adder
Sum
Cout
A
B
Cin
A
B
Sum
Carry
HAA
B
Sum
Carry
HA
Sum
Cout
A
B
Cin
A
Cin
Sum
Cout
FAB
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EECS 303 Lecture 1 26
Introduction to Mentor Graphics Tools
The Mentor Graphics CAD system has many
components
You will use a small portion of the tools for this
course
Falcon Design Framework Design Architect for entering logic designs
Quicksim for simulating the designs
QuickHDL for entering and simulating the VHDL
designs Read through and execute Lab 1: Mentor
Graphics tutorial
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EECS 303 Lecture 1 27
Introduction to Mentor Graphics
Typing source /vol/ece303/mgc.env on Sun
workstation will set up env for 303 labs
Typing dmgr for Design Manager will create a
window for running several tools
Mentor Graphics is not a single tool but a series ofdesign tools that uses object oriented data
representation to simplify the design process
Data created in one tool (e.g. design architect) can
be shipped to another tool (e.g. quicksim) forsimulation
A schematic is merely a pictorial representation of
a circuit
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EECS 303 Lecture 1 28
Viewpoints in Electronic Design Objects Data created by DESIGN
ARCHITECT is saved in
Component
Viewpoint
A component is a collection of
models used to describe the
functional, graphical aspects Component data is made of a schematic
and a symbol
A symbol is a graphical model of the
input and output pins
A schematic is a functional model of
how outputs are related to input values
A viewpoint can be thought of as a
filter that other applications use to
process component data
Component Viewpoint
Electronic Design Object
Symbol for
XOR
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EECS 303 Lecture 1 29
Moving Design Data
Students familiar with UNIX, please refrain from
using UNIX commands to move directories orfiles
You MUST move these objects using the Design
Manager
Failure to use Design Manager will result in data
corruption
Design Architect will store the absolute pathname to a
design Quicksim will try to use the symbol to look for the
design from that pathname
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EECS 303 Lecture 1 30
Summary
Class administration
Digital design methodology
Representations of Digital Design
Introduction to Mentor Graphics tools
NEXT LECTURE: Memory Elements
READING:
Chapter 4
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