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8/3/2019 PIC 54 Architecture
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PIC 16C5x
Architecture
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Architecture
RISC Processor
Harvard Architecture
Separate Buses for Program and Data Instruction size and Data size can be
different
CPU 8-bit CPU
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CPU
8-bit CPU
Dual Pipeline (Fetch and Execute)
12-bit Instruction Register
8-bit General Purpose ALU On Register File and Working Register
8-bit Working Register
STATUS Register
2 level deep H/W Stack 33 single word instructions
Single cycle instructions except program branches(two cycle)
Operating freq. DC-4MHz
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Internal Timing
PC PC+1 PC+2 PC+3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Q1
Q2
Q3
Q4
Fetch Exec
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Internal Timing
Instruction Cycle
Q1, Q2, Q3 and Q4
Fetch in one cycle Decode and Execute in the following Cycle
PC is incremented in Q1 and Fetch
Execute in the following Cycle Q1-Q4
Data Memory Read in Q2
Data Memory Write in Q4
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Memory
Program Memory - Internal
Data Memory Internal
Program Memory 512 Bytes 2K
>512, then by paging
9-bit PC
Address wraparound
Reset Vector 1FFH
NOP @ 1FFH -> restart @ 0000h
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Data Memory
Internal
Register file
General Purpose & SFR Directly or Indirectly accessible by the CPU
25 73 Bytes
7 or 8 Bytes SFR
25 or 24 general purpose registers Special Function Registers
Core
Peripheral
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PIC 16C5x Devices
PIC16C54/55/56/57/58
Difference in
No. of Pins IO
EPROM or ROM
RAM
Oscillator Selection Options
Voltage Range
MCLR Filter
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Nomenclature
PIC16xx5X:
xx Stands for
C: EPROM + Std. Op. Voltage
LC: EPROM+ Ext. Op. Voltage
CR: ROM + Std. Op. Voltage
LCR: ROM+ Ext. Op. Voltage
UV Erasable in CERDIP Package OTP One Time Programmable
QTP Quick Turnaround Production
SQTP Serialized QTP
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PIC 16C5x Family Devices
Features PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16CR56
Maximum Operating Frequency 40MHz 20MHz 40MHz 40MHz 20MHz
EPROM Program Memory
( x 12 words)512 512 1K
ROM Program Memory
( x 12 words) 512 1K
RAM Data Memory (bytes) 25 25 24 25 25
Timer Modules TMR0 TMR0 TMR0 TMR0 TMR0
IO Pins 12 12 20 12 12
No. of Instructions 33 33 33 33 33
Packages
18-pin DIP
SOIC;
20-pin SSOP
18-pin DIP
SOIC;
20-pin SSOP
28-pin DIP
SOIC;
28-pin SSOP
18-pin DIP
SOIC;
20-pin SSOP
18-pin DIP
SOIC;
20-pin SSOP
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PIC 16C5x Family Devices
Features PIC16C57 PIC16CR57 PIC16C58 PIC16CR58
Maximum Operating Frequency 40MHz 20MHz 40MHz 20MHz
EPROM Program Memory
( x 12 words)2K 2K 1K
ROM Program Memory
( x 12 words) 2K 2K
RAM Data Memory (bytes) 72 72 73 73
Timer Modules TMR0 TMR0 TMR0 TMR0
IO Pins 20 20 12 12
No. of Instructions 33 33 33 33
Packages
28-pin DIP
SOIC;
28-pin SSOP
28-pin DIP
SOIC;
28-pin SSOP
18-pin DIP
SOIC;
20-pin SSOP
18-pin DIP
SOIC;
20-pin SSOP
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Oscillator Options
RC Resistor/Capacitor
XT Standard Crystal/Resonator
HS High Speed Crystal/Resonator
LP Power Saving Low Frequency Crystal
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Reset Options
Power On Reset (POR)
/MCLR reset (Normal Operation)
/MCLR wake-up reset ( from SLEEP)
WDT reset ( Normal Operation)
WDT wake-up Reset (From SLEEP)
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Peripherals
8-bit Timer/Counter with 8-bit Prescalar
Power On Reset
Device Reset Timer (DRT)
Watch Dog Timer
Code Protection
SLEEP Mode
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Ports
RA 4 Bits
RB 8 Bits
RC 8 Bits Additional Pins
CLKIN
CLKOUT
/MCLR/Vpp
T0CKI
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Application of PIC
Applications requiring
Small Size
High Speed Low Power
IO Flexibility
Application Areas
Automation
Motor Control
Remote Transmitter/Receiver
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STATUS
Address 7 6 5 4 3 2 1 0
03H PA2 PA1 PA0 /TO /PD /Z /DC C
TO Time out
0 WDT Time out
1 After power u p by CLRWDT/SLEEP
PD Time out
0 SLEEP
1 After power u p by CLRWDT
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OPTION
Timer0 CLK Source
1 = TOCKI pin
0 = CLKOUT
Timer0 CLK Edge Select
0 = at TOCKI pin
1 = at TOCKI pin
Address 7 6 5 4 3 2 1 0
- - T0CS T0SE PSA PS2 PS1 PS0
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OPTION
Prescalar Assignment Bit
1 = Prescalar to WDT
0 = Prescalar to Timer0
Address 7 6 5 4 3 2 1 0
- - T0CS TOSE PSA PS2 PS1 PS0
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OPTION
Prescalar Rate Select BitsBit Value Timer0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1:16 1:8
100 1:32 1:16
101 1:64 1:32
110 1:128 1:64
111 1:256 1:128
Address 7 6 5 4 3 2 1 0
- - T0CS TOSE PSA PS2 PS1 PS0
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IO Ports
Port A at 05H
4 bit I/O Register
Port B at 06H 8 bit I/O Register
Port C at 07H
8 bit I/O Register for16C55, 16C57 and 16CR57 8 bit General Purpose Register for16C54,
16CR54, 16C56, 16CR56, 16C58 and 16CR58
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TRIS Register
Tri-state Register
O/p driver control register
Sets the Direction of the IO pins 1 puts the pin in Hi-Impedance Mode
0 puts the contents of the output data latchon the selected pins
Write Only At reset TRIS are set and all I/Os in I/P mode
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IO Ports
All Pins are individually Programmable
Write to Latch
The data remain unchanged until rewritten
Read from Pin
Not latched, The data must be present until
read by an instruction.
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TIMER0
8-bit Timer Counter register
Readable and Writable
8-bit software programmable Prescalar Set by OPTION Register
Internal Or External Clock Select
Rising or Falling Edge Select for ExternalClock
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TIMER0
External Clock requirements
External Clock Synchronization
Sampling the PreScalar output on Q2 and Q4 T0CKI High for at least 2 TOSC
T0CKI Low for at least 2 TOSC
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Prescalar Unit
8-bit Counter
Available to Timer0 or WDT
The divide Down Ratio is Selected byOPTION register
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PreScalar Assignment
Changing Prescalar from WDTp Timer0
Clear WDT
Load Desired Prescalar value for the Timer0
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PreScalar Assignment
Changing Prescalar from Timer0pWDT
Clear WDT
Clear TMR0 Load Maximum Prescalar Value
Clear WDT
Load Desired Prescalar value for the WDT
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STACK
9/10/11 bit two level stack h/w stack
CALL -> PUSH STACK1 -> STACK2;
PC -> STACK1
RETLW ->
STACK1 -> PC;
STACK2 -> STACK1
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