3456 3; &./0(+/1%blj/CS-590.26/lectures/LectureG.pdf · 0 3456 3;? c 2$ 1/) 3 kd 953a+b=9.89!" &!’ & * & 9 < =;"> =?> =;@> =;’> =;a> =a> i-/, i =*k>

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!5

GKILJM'INO!PQ!+RMO<RKD

!"#$%&'()*+",-./0+(&12!"#$%&'(()%*(+,-.%&./0(+/1%2-3$"0(304-(%56)%7(-8,-+563(%2659./"/:"-(/;%&"#6599"6#;%56)%<"+"6#%

!-34.5+673-3+8-34.5+.9+4:3S!'T#*)0!=-21B#2!-.#$#2BT!B.1U-.V!WX!AB=-CY!FB2$!3448Z!

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!3


;<.0.5=>?+"@953A+B=9.89

!"#$#%&

!'#$#%&

()!*

+,-#&..-,//0-,&

*12/3*4./156&,7$#&/25869

:;<

=;">

=*?>

=;@>

=;'> =;A>

=*@>

=*A>

=*'>

=*">

1BC/6-/D&D-,E/6,$778# D&D-,E/,&F4&.6/.#%&G4H85I

J%E.8#$H/6-/D&D-,E/$GG,D$JJ85I =*K>

=*L>

,&$GG$6$M477&,

.E.6&D/#-56,-HH&,

J,-#&..-,

(:;</#-,&

=*N>

+$,6/;O/P&$,#%85I-5Q#%8J/7-,/G$6$

+$,6/*O/R-85I-77Q#%8J/7-,/G$6$

<=5=+5-=/9,C-5+9,334C/+9@953A+DC=-4+4C39+/C5+98=>3+6'-'5'+ECC-3F9+G=6'

!7.,+,3-HC-A=/8398=>./0+6.57+-39,3855C+ECC-3F9+G=6

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ![


IC6+<C+J3+KC+;L=953-?M

RS!N.B20B=1#-2!.)\>)01!,B/!C)!*)TB/)*!#2!]>)>)@S!N.B20B=1#-2!.)\>)01!0)21!1-!+),-./!7-21.-TT).7S!N.B20B=1#-2!=-2E).1)*!1-!7-,,B2*!')\>)2=)0

W,B/!C)!\>)>)*ZDS!7-,,B2*^0!')21!1-!DMR+J5S!M)\>#.)0!-2T/!B!!N"!-.J3S!M)\>#.)0!ON"+P+!N"!-.QS DB1B!#0!01B$)*!B1!7-21.-TT).

_DMR+!<B1)2=/`!a!R!b!@!b!7!b!D!b!J!b!Q!b!?

J[S!M)\>#.)0!QOR+P+ON"+P+!N"

L=953-+GC0.8

L=953-+J.-39

L=953-+<ONE+!.-8:.59

@7 D

DMR+

J3^J[

J5

?

R

7cG +),7-21.-TT).

Q

?S!N.B20B=1#-2!0)21!CB=V!1-!7cG

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!6


Q-C5C8C>+;RHH.8.3/8@?

! " # $ % &

'()*+,+#

!>S!>S+T

-./.

-0)

'12

-0)+3456.1785 -0)+39:/6.1785

4!

; < =

2"

4"

2"2"2"2!2!2!2!

-5.2+'>?85

@.?A6/967.?A+45.2:+/9+2BCC545D/+4.DA:

'.D+E5+1.A5+/F5+?>?85:+:1.8854G

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!;


"A=>>3-+!@8>3+U.A3+B:4035M

O.93+U.A3

VW3-97CC5

"355>3+U.A3

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!d


N+".0/=>./0+"@953A

($6$/15($6$/-46

3J-856/;9 3J-856/*9

S,&7

!"#$%&'%%'($)*'$+,- .

/

0

!"#$%&'11+"

23(45'$6)&+47#$'%&

8+4+'9+"

!+"&'$#1("

T/+-4H6-5/1PP00/"UUU/P8I5$H85I/)46-,8$H

1'+U-=/9A.553-X+R/8C439+4=5=+=9+8:--3/5YWC>5=03+>3W3>+

('+U-=/9A.99.C/+G./3X+<3>.W3-+4=5=+H-CA+5-=/9A.553-+5C+

Z'+O383.W3-X+!CA,=-3+=0=./95+-3H3-3/83+5C+3[5-=85+4=5=

2'+U3-A./=5C-X+O3ACW3+9.0/=>+H-CA+>./3*+C/83+573@F-3+

C/5C+573+>./3

-383.W3-

-383.W34$'+!>C8SX+U3>>9+5-=/9A.553-+673/+5C+93/4*+-383.W3-+673/+

5C+9=A,>3+9.0/=>

ENEE 359aLecture/s 10+11

Interconnects

Bruce Jacob

University ofMaryland

ECE Dept.

SLIDE 1

UNIVERSITY OF MARYLAND

ENEE 359a

Digital Electronics

Interconnects

Prof. Bruce [email protected]

Credit where credit is due

: Slides contain original artwork (© Jacob 2004) as well as material taken liberally from Irwin & Vijay’s CSE477 slides (PSU), Schmit & Strojwas’s 18-322 slides (CMU), Dally’s EE273 slides (Stanford), Wolf’s slides for

Modern VLSI Design

, and/or Rabaey’s slides (UCB).


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 2


Overview

•

Wires and their physical properties(MOSFETs, too …)

•

LC/RC/RLC transmission lines, characteristic impedance, reflections

•

Dynamic considerations (e.g. skin effect)

•

The Bottom Line: propagation delay, transistor sizing, inductive (Ldi/dt) noise, capacitive coupling, signal degradation, various rules of thumb for design


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 3


Metal Layers in ICs

IBM’s 6-layer copper interconnect


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 4


Some Transmission Lines

Insulating jacketOuter shieldInner dielectricInner conductor

Coaxial Cable

Twisted Pair

dielectricconductor

dielectricconductor

Microstrip

Stripline

Gnd

Gnd

dielectric

dielectric

Gnd

conductor

conductor


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 5


Cross Section of PCB Board

FR4 DielectricM1 (signal layer)

M2 (Ground plane)

M3 (Power plane)

M4 (signal layer)

FR4 DielectricM1 (signal layer)

M2 (Ground plane)

M5 (Power plane)M6 (signal layer)

M3 (signal layer)M4 (signal layer)


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 6


Wires in Digital Systems

Physically, wires are

• Stripguides on (and

in

) printed circuit-board cards, layed over & sandwiched between groundplanes

• Stripguides on ICs, layered atop each other• Conductors in cables & cable assemblies• Connectors

We tend to treat them as

IDEAL wires

• No delay (equipotential)• No capacitance, inductance, or resistance

They are

NOT

ideal …

To build reliable systems, must understand properties & behavior


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 7


Metal Layers in ICs

Remember the

RC Constant

ττττ

?

p-tub

poly poly

n+n+

metal 1

metal 3

metal 2

vias


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 8


Metal Layers & Capacitances

• On-chip wires run in multiple layers with no explicit return planes (ground is used as implicit return)

• Thus, almost all capacitance of on-chip wire is to

other wires

(same plane, different plane, etc.)• Capacitance of MOSFET scales with Vdd

p-tub

poly poly

n+n+

metal 1

metal 3

metal 2

vias


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 9


Metal Layers & Resistances

• Resistance of conductor proportional to length/width, depends on material (resistivity), causes delay & loss

• Resistance of wire scales with square root of signaling frequency (at high speeds) (“skin effect”)

• Process scaling tends to increase resistance

p-tub

poly poly

n+n+

metal 1

metal 3

metal 2

vias


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 10


Wire Resistance

•

R =

ρρρρ

l/A =

ρρρρ

l/(wh) for rectangular wires(on-chip wires & vias, PCB traces)

•

R =

ρρρρ

l/A =

ρρρρ

l/(

ππππ

r

2

) for circular wires(off-chip, off-PCB)

Material Resistivity

ρρρρ

(

ΩΩΩΩ

-m)

Silver (Ag) 1.6 x 10-8Copper (Cu) 1.7 x 10-8Gold (Au) 2.2 x 10-8Aluminum (Al) 2.7 x 10-8Tungsten (W) 5.5 x 10-8

hw

l l

r


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 11


Sheet Resistance

R =

ρρρρ

l/(wh) = l/w•

ρρρρ

/h for rectangular wiresSheet resistance R

sq

=

ρρρρ

/h

Material Sheet resistance R

sq

(

ΩΩΩΩ

/sq)

n, p well diffusion 1000 to 1500n+, p+ diffusion 50 to 150polysilicon 150 to 200polysilicon with silicide 4 to 5Aluminum 0.05 to 0.1


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 12


Wire Capacitance

Common wire cross-sections/permittivities:

• Permittivity

εεεε

=

εεεε

0

εεεε

r

• Permittivity of free space

εεεε

0

= 8.854 x 10

-12

F/m

h

Material

εεεε

r

Air 1Teflon 2Polymide 3SiO

2

3.9

Glass-epoxy (PCB)

4

Alumina 10Silicon 11.7


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 13


Inductance

When conductors of transmission line are surrounded by uniform dielectric, capacitance & inductance are related:

CL =

εεεε

µ

Inductive effects can be ignored

• if the resistance of the wire is substantial enough (as is the case for long Al wires with small cross section)

• if rise & fall times of applied signals are slow enough

So … inductance must be considered

• for off-chip signals (even power/ground)• for future even-higher-speed on-chip signalling


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 16


Wires & Models

Example Wires:

In a situation, use a

model

of wires that captures the properties we need:

• ideal, lumped L, R, or C• LC, RC, RLC transmission line• General LRCG transmission line

Appropriate choice of model depends on signaling frequency

Type W R C L

On-chip 0.6 µm 150k

ΩΩΩΩ

/m 200 pf/m 600 nH/mPC Board 150 µm 5

ΩΩΩΩ

/m 100 pf/m 300 nH/m24AWG pair 511 µm 0.08

ΩΩΩΩ

/m 40 pf/m 400 nH/m

f

0

R

2

π

L

----------=


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 17


General LRCG Model

Model an

infinitesimal

length of wire, dx, withlumped componentsL, R, C, and G

(inductance, resistance,capacitance, and conductance)

x

2

2

∂

∂

V RC t

∂∂

V LCt

2

2

∂

∂

V

+=

x

∂∂

V RI L t

∂∂

I

+=

Drop across R and L

x

∂∂

I GV C t

∂∂

V

+=

Current into C and G

x

2

2

∂

∂

V RGV RC LG

+

( )

t

∂∂

V LCt

2

2

∂

∂

V

+ +=

For G=0:


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 18


Impedance

• An infinite length of LRCG transmission line has

impedance Z

0

• Driving a line

terminated

into Z

0

is same as driving Z

0

• In general, Z

0

is complex and frequency-dependent• For LC lines (operating at “high” frequencies), Z

0

is real-valued and independent of frequency

s = 2

π

jƒ = j

ω

(typical assumption: G = 0)


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 19


Cut-off Frequency f

0

R dx L dx

C dx G dx

R dx L dx

C dxC dx

Z

0

=

R +

j

ωωωω

L

G + j

ωωωω

C

1

2

Z

0

“lossless” LC “Low” FreqR >> j

ωωωω

L R << j

ωωωω

L

find f

0

where

R ==

j

ωωωω

L

“High” Freq

- Transmission lines have characteristic frequency f

0

- Below f

0

≈≈≈≈

RC model, Above f

0

≈≈≈≈

LC model

f

0

R

2

π

L

----------=

Z

0

Rj

ω

C

-----------=

Z

0

LC

----=


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 20


Cut-off Frequency f

0

Frequency


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 21


Cut-off Frequency f

0

II

Z

0

=

L

C

1

2

0.5 nH

0.1 pF

1

2= ~= 70

ΩΩΩΩ

Example from Poulton 1999 ISSCC Tutorial

L = 0.6 nH/mmC = 73 nF/mmR

dc

= 120

ΩΩΩΩ

/mmf

0

= 32 GHz

L = 0.5 nH/mmC = 104 fF/mmR

dc

= 0.008

ΩΩΩΩ

/mmf

0

= 2.5 MHz

~LC Model for PC Board

FR4 Dielectric

SiO

2

traces~RC Model for on chipinterconnects

0.5

µµµµ

0.5

µµµµ

0.7 mil5 mil

1 mil = 0.001 inch


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 22


RC Lines (low frequency)

R >> j

ωωωω

L, governed by diffusion equation:

Signal diffuses down line, disperses:

x

2

2

∂

∂

V RGV RC LG

+

( )

t

∂∂

V LCt

2

2

∂

∂

V

+ +=

V

2

∂

x

2

∂

---------

RC V

∂

t

∂

-------=

0mm

2.5mm

5mm

7.5mm

10mm

R increases w/ length dC increases with dDelay & rise time both

increase with RC, thus with d

2

For a typical wire:R = 150K

ΩΩΩΩ

/mC = 200pF/m

ττττ

= RC = 30 µs/m

2

= 30 ps/mm 2


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 23


LC Lines (high frequency)

R << j

ωωωω

L, governed by wave equation:

Waveform on line is superposition of forward- and reverse-traveling waves:

• Waves travel with velocity v = (LC)

-1/2

• What happens when the wave gets to the end of line?

x

2

2

∂

∂

V RGV RC LG

+

( )

t

∂∂

V LCt

2

2

∂

∂

V

+ +=

V

2

∂

x

2

∂

---------

LC V

2

∂

t

2

∂

---------=

V

i

x t

,

( )

Z

0

Z

0

R

S

+-------------------

V

S

t xv

---–

=

V

f

V

r


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 24


RLC/G Lines (general case)

Ignoring G, wave propagation equation:

Lossy transmission line, dispersive waves:

x

2

2

∂

∂

V RGV RC LG

+

( )

t

∂∂

V LCt

2

2

∂

∂

V

+ +=

V

2

∂

x

2

∂

---------

RC V

∂

t

∂

-------

LC V

2

∂

t

2

∂

---------+=

Substrate-doping-dependent dispersion of a picosecond-scale pulse in propagation of an on-chip transmission line


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 25


RC vs. RLC

Output response of inverter with step input:

In reality, we have a non-zero inductance in series with the RC circuit. (Inductors and capacitors both “have memory”)

VDD

?

L

VDD

L

GND

R

n

R

p

C

in


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 26


RC vs. RLC

Output response of inverter with step input:

Result: slower reponse time, ringing

0

Vdd

V

tl

RC ModelRLC Model

tens of ps

inductor causes slow start-up for switch


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 27


Impedance and Reflections

Terminating a Transmission Line:

Telegrapher’s Equations:

Reflection coefficient k

r

may be complex for complex impedances Z

T

— i.e., the reflected wave may be phase-shifted from the incident wave. For real-valued Z

T

the reflection coefficient is real, and the phase shift is either 0 (k

r

positive) or

ππππ

(k

r

negative).

V

i

Z

0

Z

T

I

f

I

r

I

T

k

r

I

r

I

i

----

V

r

V

i

------

Z

T

Z

0

–

Z

T

Z

0

+-------------------= = =


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 28



Z

0

Z

0

V

A

V

C

V

B

k

r

I

r

I

i

----

V

r

V

i

------

Z

T

Z

0

–

Z

T

Z

0

+-------------------= = =

Va

Vb

Vc

Z

0

Va

Vb

Vc

Z

T

=

∞∞∞∞

Z

0

Va

Vb

Vc

Z

T

= 0

Matched Termination, k

r

= 0

Open-Circuit Termination, k

r

= 1

Short-Circuit Termination, k

r

= -1


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 29



50

ΩΩΩΩ

, 5ns

1K

ΩΩΩΩ

1V

400

ΩΩΩΩ

RS


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 30



Values are typical for 8-mA CMOS driver with 1k

ΩΩΩΩ

pullup

50

ΩΩΩΩ

, 5ns

1K

ΩΩΩΩ

1V

400

ΩΩΩΩ

RS

V

i

Z

0

Z

0

R

S

+-------------------

V

S

5050 400+---------------------

1

V

0.111

V

= = =

k

rR

Z

T

Z

0

–

Z

T

Z

0

+------------------- 1000 50–

1000 50+------------------------ 0.905= = =

k

rS

Z

T

Z

0

–

Z

T

Z

0

+------------------- 400 50–

400 50+--------------------- 0.778= = =


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 31



Vwave Vline time t

Vi1 0.111 0.111 0Vr1 0.101 0.212 5Vi2 0.078 0.290 10Vr2 0.071 0.361 15Vi3 0.055 0.416 20Vr3 0.050 0.465 25Vi4 0.039 0.504 30Vr4 0.035 0.539 35Vi5 0.027 0.566 40

50

ΩΩΩΩ

, 5ns

1K

ΩΩΩΩ

1V

400

ΩΩΩΩ

RS


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 32



50

ΩΩΩΩ

, 5ns

1K

ΩΩΩΩ

1V

400

ΩΩΩΩ

RS

TIME

Vline


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 33


Reflections, Z

S

< Z

0

Z

L

Z

S

Z

S

= 25

ΩΩΩΩ

Z

0

= 50

ΩΩΩΩ

V

I

V

I

= 0v 2v

Z

0

TD = 250 ps

V

S

V

S

= V

I

V

L

Z

S

Z

S

+ Z

0

= 2 * 50

25 + 50= 1.3333 V

Z

L

= inf

ΩΩΩΩ

k

r (source)

=Z

S

- Z

0

Z

S

+ Z

0

= 25 + 5025 - 50

= - 0.3333

k

r (load)

=Z

L

- Z

0

Z

L

+ Z

0

= inf + 50inf - 50

= 1


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 34


Reflections, Z

S

< Z

0

Z

L

Z

S

V

I

Z

0

TD = 250 ps

V

S

V

L

Time (ps)

0

V

S

V

L

0 v

250

1.33 v

k

r (source)

= - 0.3333k

r (load)

= 1

1.33 v1.33v

2.66 v-0.443 v

-0.443 v

0.148 v

2.22v

1.77v

500

750

1000

1.92v


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 35


Reflections, Z

S

< Z

0

Time (ps)

Volts

0 250 500 750 1000 1250 1500

0.5v

1.0v

1.5v

2.0v

2.5v

1750

V

load

V

source


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 36


Add In Capacitance …

50

ΩΩΩΩ

, 5ns

1V

50

ΩΩΩΩ

RS

TIME

Vline

What if we throw in a capacitor (i.e., reality?)Simple case: matched impedance at source end

Source end

Receiving end


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 37



Modern systems have MANY, MANY, MANY potential sources of impedance-mismatch and/or reflections

CPU Mem Contr.

DIMMs

DRAMs

PCB Traces

Package Pins& Connectors

Electrical connectionsover physical contacts

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!K8

GLIMJN'IOP!QR!+SNP<SLD

!"#$%&'()*+",*-

!"#$%&'()*)+

!"#$%&'()*),

!"#$%&'()*)-

.(//01$('*&%,1(/$%/"%$2

3'4/,5%,,%(/#%/0*6"4#%$2&0)0/&,*(/,2,$05*7(4'&

8419*%5)0&4/10*&%,1(/$%/"%$2*%,*4*'0:#01$%;0*%/$0':410

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!K;


!"#$%&'()*+",*--

!"#$% &$%#$%'(

!"#$% &$%#$%')

!"#$% &$%#$%'* &$%#$%'*

&$%#$%')

&$%#$%'(

+&,-',!".!".

/0,.-,'1-/02/&3-,',!4-%!+-

Memory SystemsArchitecture and

PerformanceAnalysis

Spring 2005

ENEE 759HLecture13.fm

Bruce JacobDavid Wang


ECE Dept.

SLIDE 40


Capacitive Termination I

ZLZSVI

Z0VS VL

- Capacitors behave like short circuit when

ZL = 0; Short Circuit ρ = 0 - ZS0 + ZS

ρ = -1

ZL = inf; Open Circuit ρ = ZLZL

ρ = 1

not charged. Once charged, behaves likeopen circuit.

Bruce Jacob

k

Bruce Jacob

k

Bruce Jacob

k

Bruce Jacob

k

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!65


!=,=8.5.W3+U3-A./=5.C/+\\

]G]"^\+

]&^"+ ^G+

^G+^G+

^" ^"

#+J73/+;97C-534?*+^"+.9+-3H>38534+6.57+573+9=A3+A=0/.5:43+D=8S+5C6=-4+9C:-83'

#+U73+;A=0/.5:43?+73-3+.9+573+;A=0/.5:43?+

5.A35.A3

#+UC+A./.A._3+0>.587*+>.A.5+9>36+-=53'CH+-.93+5.A3'


PerformanceAnalysis

Spring 2005




ECE Dept.

SLIDE 42


What is a Stub?

Z0 = 50 Ω

GND

5nH

2 pF0.2 pF75Ω50 Ω

trace50Ω

pkg

bondwire

pad& rx

Stub

- Signal path inside of package also significant

trace

terminatingresistor


PerformanceAnalysis

Spring 2005




ECE Dept.

SLIDE 43


Series Stub Terminated Logic

Z0 = 50 Ω

GND

5nH

2 pF0.2 pF

bondwire

pad& rx

seriesresistor

Reflection Coefficient = ρ = ZL - ZSZL + ZS

25 Ω

ρ = 25 - 5025 + 50

= - 0.3333

- Series resistor isolates stub from line- reduces ringing- reduces power

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!66


O=AD:9+".0/=>>./0

'9D/498854

2424.18>C8S5:-/9=-C:/4 ?FB3

2424.1?FB3

2424.1?FB3

/541BD./B9D/541BD./B9D

#+!C/5-C>>3-+93/49+H:>>+73.075+9.0/=>+96./09#+<ONE+87.,9+93/4+7=>H+73.075+9.0/=>+96./09#+O3H>385.C/+CHH+CH+8C/5-C>>3-+4-.W3-+

`C,3/+8.-8:.5 53-A./=534

8-3=539+H:>>+73.075+9.0/=>+96./0

#+!:--3/5+AC43

#+!:--3/5+8C/5-C>+=/4+WC>5=03+9>36-=53+8C/5-C>

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!68


O=AD:9+!7=//3>+#+1)+D.5/

!>C8S

U3-A./=5.C/

!C/5-C>>3-

O\EE

O\EE

"@953A+BC=-4

"@953A+BC=-4

#+O\EE+TZ+4-C,,34+H-CA+9,38+5C+9C>W3+9.0/=>>./0+,-CD>3A9#+a334+!C/5./:.5@+O\EE

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!6;


O=AD:9+!7=//3>+#+Z(Y)2+D.5/

!>C8SU3-A./=5.C/O\EE

"@953A+BC=-4"@953A+BC=-4

!C/5-C>>3-

#+U3-A./=5.C/+D-C:075+C/5C+O\EE#+!C//385C-+./53-H=83+8C:/5+-34:834+H-CA+2+5C+Z#+aC+/334+HC-+9,38.=>+53-A./=534+O\EE+=/4+/C/#53-A./=534+O\EE

O\EE

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!6d


V<UX+V/+<.3+U3-A./=5.C/^44b ^44b

^99b ^99b

<ONE+./,:5D:HH3-

"J1

"J1 "J(

"J(

OW=>1

OW=>1 OW=>(

OW=>(

<ONE<c+./,:5,./

#+N85.W3*+4@/=A.8+53-A./=5.C/*+43,3/4./0+C/+OYJ*+=/4/:AD3-+CH+>C=49+C/+3>385-.8=>+D:9

#+!=/+D3+5:-/34+C/YCHH+./+(+8@8>39*+CHH+./+('$+8@8>39#+<39.0/34+./5C+<<O+\\

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!6e


\/,:5+B:HH3-./0+#+O3H3-3/839+\

^C:5^./

Z'ZZ'&

('&

1'&

('&1'& Z'& Z'Z./,:5+WC>5=03

^./+>C6+d+&'e^ ^./+7.07+d+('&^

^C:5+7.07+d+('2^

^C:5+>C6+d+&'2^

G^UUG

C:5,:5WC>5=03

./W3-53-

".A,>3+\/W3-53-

./,:5WC>5=03

C:5,:5WC>5=03

^C:5^./

('$

('&

1'&

('&1'& ('$./,:5+WC>5=03

^./+>C6+d+

^C:5+>C6+d+&'ZfZ^

""UG#(C:5,:5WC>5=03 ./W3-53-

^-3H+#+&'1$W^./+I.07+d+^-3H+P+&'1$W

gH:>>+8:--3/5+4-.W3h

^C:5+>C6+d+^44b+#+&'ZfZ^gH:>>+8:--3/5+4-.W3h

./,:5WC>5=03

C:5,:5WC>5=03

W-3H

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!69


\/,:5+B:HH3-./0+#+O3H3-3/839+\\

W-3H

^88

K/4

WC:5W./

#+GC8=>+C-+-3AC53+-3H3-3/83M#+\/W3-53-9+=-3/F5+W3-@+0CC4+HC-+7.07+H-3b:3/8@+9.0/=>>./0

W./& W&W./1

W./(W./Z

W1

W(

WZ

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!84


<.HH3-3/5.=>+".0/=>>./0

#+U73+8CA,>3A3/5+9.0/=>+,=57+.9+573+8:--3/5+-35:-/+,=57#+"3/4+573+9.0/=>+=/4+.59+8CA,>3A3/5

W./&+P W&W./1+P

W./(+PW./Z+P

W1

W(

WZ

W./&+#

W./1+#

W./(+#W./Z+#

#+".0/=>+,=.-9+A:95+D3+-C:534+8>C93>@+5C03573-#+".0/=>>./0+9873A3+8=/+-3i385+8CAAC/+AC43+/C.93b:.53+63>>


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 46


Inductive Noise

L di/dt noise (ground bounce):

VDD

IDEAL

Current flow changes directionwhen input (thus output) values change

VDD

REALISTIC

L

(

≠

0)

L

(

≠

0)

Magnitude of current change is diThe time to switch directions is dtThe voltage-drop induced on this wireat time of switching is L di/dt


Interconnects

Bruce Jacob


ECE Dept.

SLIDE 47


Inductive Noise

L di/dt noise (ground bounce):

VDD

L

(

≠

0)

L

(

≠

0)

∆∆∆∆

V = L di/dt = voltage-drop

∆∆∆∆

V

∆∆∆∆

V

induced on this wire

VDD

“1” Another inverter, elsewhere.What comes out here?

I/O Driver:

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!8


O3=>+W9+\43=>+JC->4

jUC97.D=+Q-393/5=5.C/*+<3/=>.+E3A!C/+(&&(

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!K


!"#$%&'($&%"#)*+,-

!"#"$%&!"#"$'(#

)*'+&#$,- )*'+&#$.-

/012

!"#$%&'%%'($)*'$+,- .

/

0

!"#$%&'11+"

23(45'$6)&+47#$'%&

8+4+'9+"

!+"&'$#1("

3$4'(5#'&$%6677$8999$6+:&"5+&:$;(#'0+"5

./"01'&*-$++,12"3&456,*"6'+'"'*"4711,&+895(+'%,"(,9,("

:/"01'&*-$**$5&";$&,2"<,($9,1"6'+'"=15-"+1'&*-$++,1"+5"

>/"?,4,$9,12"@5-A'1,"'%'$&*+"1,=,1,&4,"+5",B+1'4+"6'+'

C/"0,1-$&'+512"?,-59,"*$%&'("=15-"($&,D"5&4,"+E,)F1,"

5&+5"+E,"($&,

1,4,$9,1

1,4,$9,6G/"@(54H2"0,((*"+1'&*-$++,1"IE,&"+5"*,&6D"1,4,$9,1"IE,&"

+5"*'-A(,"*$%&'(

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!54


U.A./0+B:4035+^.9:=>._34($6$/15

($6$/-46

3J-856/;9 3J-856/*9

S,&7

!"#$%&'%%'($)*'$+,- .

/

0

!"#$%&'11+"

23(45'$6)&+47#$'%&

8+4+'9+"

!+"&'$#1("

ENEE 359aLecture/s 16-19

System Timing

Bruce Jacob


ECE Dept.

SLIDE 12


Definitions:

Skew

SubChannel 1

SubChannel 2

- Static timing displacement from ideal design

clock - clock skew

- Caused by differences in signal path characteristics - Total timing budget must take data-data skew,

data-clock skew as well as clock-clock skew intocycle budget consideration

data - data skew

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!5K


!"#$%&'()#$%*+,,'-'(#+".

!"#$%&#''(&

)*%+,-.)*%+,-/

)*%+,-0

123,456$*',/123,456$*',0

7$%(&8#92'(,"#$$(:%#&3

1


System Timing

Bruce Jacob


ECE Dept.

SLIDE 13


Definitions:

Jitter

- Dynamic timing displacement from nominal timingcharacteristics

- Magnitude and offset of timing displacement could depend on: previous signal state(s), current signal state(s), supply voltage level(s), crosstalk, variationsin thermal characteristics. Perhaps even phases of the moon (not proven).

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!56


!"#$%&'("&)*++*,'-

./012'""$3*4

./012'""$3*5

67%8&*1'8$89$:*7;*<12'"*4*=12'"*5>

67%8&*1'8$89$:*7;*12'"*4*

67%8&*1'8$89$:*7;*12'"*5

67%8&*#'8$*89$:*?/8&*0$*#7"8(-$%$-*("*8)8&$?*&(?("@

137#9*.9$:


System Timing

Bruce Jacob


ECE Dept.

SLIDE 53


Global Clock I

D Q

Clock

DataD Q

Transmitter Receiver

1

2 3

4

50

0

1

4

2

3

5

0: Assume data is stable for setup time before clock edge1: Rising edge of transmitter clock2: Transmitter begins to drive data (perhaps through logic)3: Signal reaches input of receiver.4: Rising edge of receiver clock5: Receiver latches data and drives internal signal lines


System Timing

Bruce Jacob


ECE Dept.

SLIDE 54


Global Clock II: Parallel Data

D QData

D Q

Transmitter Receiver

2” 3” 5”0”

0’ & 0“

1’ & 1”

2’ & 2”

3’ & 3”

D Q

ClockData

D Q

1’

2’ 3’

4’

5’0’

5’ & 5”

4”1”

transmitter input

transmitter clock

transmitter output

receiver input

receiver output

4’ & 4”receiver clock

- Skew and jitter eats into timing budget- Luckily, uncertainty does not accumulate beyond latches


System Timing

Bruce Jacob


ECE Dept.

SLIDE 3


What Needs To Be Done?

By the way: “global” clock scheme

ClkSRC


System Timing

Bruce Jacob


ECE Dept.

SLIDE 4


Background: Elmore Delays

ClkSRC

R

1

C

1

R

2

C

2

R

4

C

4

R

3

C

3

τ

Di

C

k

R

ikk

1=

N

∑

=

N

1

N

2

N

4

N

3


System Timing

Bruce Jacob


ECE Dept.

SLIDE 5


Background: Elmore Delays

ClkSRC

1 1

1 1

1 1

1

1

τ

Di

C

k

R

ikk

1=

N

∑

=

ττττ

D1

= 4

ττττ

D2

= 5

ττττ

D3

= 6

ττττ

D4

= 7

C

1

+C

2

+C

3

+C

4

C

1

+2C

2

+C

3

+C

4

C

1

+C

2

+2C

3

+2C

4

C

1

+C

2

+2C

3

+3C

4


System Timing

Bruce Jacob


ECE Dept.

SLIDE 6


End Result:

Clock Skew

In general, even nearby clocks not in synch

ClkSRC

1 time unit


System Timing

Bruce Jacob


ECE Dept.

SLIDE 59


Clock Tree I

• Every branch sees same wire length and capacitance• The clock skew is theoretically zero• The sub-blocks should be small enough s.t. the skew

within the block is tolerable• Essential to consider clock distribution

early

in the design process

Clock distributionis a

major

design problem!


System Timing

Bruce Jacob


ECE Dept.

SLIDE 60


Clock Tree I

An on-chip clock tree


System Timing

Bruce Jacob


ECE Dept.

SLIDE 61


Clock Tree II (I with buffers)

- Large synchronous systems require all components (chips or registers) to be driven by clock signal.

- Clock signal paths and buffers could introduce both skew and jitter at each stage

- Jitter and skew are additive with larger systems. More buffering, more skew and jitter.

buffer chipscould have +/-xx% tolerance


System Timing

Bruce Jacob


ECE Dept.

SLIDE 62


DEC Alpha 21164

9.3 M Transistors, 4 metal layers, 0.55µmClock Freq: 300 MHz Clock Load: 3.75 nF Power in Clock = 20W (out of 50W) Two Level Clock Distribution:• Single 6-stage driver at center• Secondary buffers drive left and right sideMax clock skew less than 100psec• Routing the clock in the opposite direction• Proper timing


System Timing

Bruce Jacob


ECE Dept.

SLIDE 63


Clock Skew in Alpha


System Timing

Bruce Jacob


ECE Dept.

SLIDE 65


Phase Locked Loop

- Given a data signal, recover the frequency and phase of

φφφφ

out

VCO

D

Freq/Phase

LoopFilter

the data signal, generate local reference clock

φφφφ

out

- Local reference clock may be frequency multiple of input clock

- PLL depends on data input to provide “enough” signal transitions to lock onto, else PLL could lose coherency.

- Modern processors utilize PLL’s for frequency multiplication


System Timing

Bruce Jacob


ECE Dept.

SLIDE 66


Voltage Controlled Oscillator

Ring Oscillator

- VCO may be designed from ring oscillator where voltage controls the number of (odd) stages of inverters in the feedback ring

LC Oscillator (conceptual illustration)

- VCO may be designed from resonant oscillator where voltage controls capacitance in LC circuit.

C(v)

L


System Timing

Bruce Jacob


ECE Dept.

SLIDE 67


Delay Locked Loop

- Given a data signal and reference clock, compare

φφφφ

out

D

PhaseComp

LoopFilter

and adjust phase of local clock signal by

∆∆∆∆φφφφ

- Unlike PLL, requires reference clock

- Modern DRAM with dual edged clocking utilizes

φφφφ

r

∆∆∆∆φφφφ

DLL’s for phase compensation. (gets you 90 degrees)

- Hence, no need to “recover” clock signal with VCO


System Timing

Bruce Jacob


ECE Dept.

SLIDE 68


Zero-Skew Clock Distribution

PLL

or

DLL


System Timing

Bruce Jacob


ECE Dept.

SLIDE 69


DLL in DDR SDRAM

DRAMArray

CK

EXT

DQ

EXT

This represents a delay

D

of the clock signal

Data

from clock input pad to data output drivers

D

Additional delaythrough DQ drivers

READ

Ideally, these two edgeswould be aligned

DRAMArray

DQ

EXT

This represents a delay

D

of the clock signal

Data

from clock input pad to data output drivers

Delay

PhaseComp

Filte

r

The Phase Comparison, Loop Filter, and Variable Delay components constitute a DLL

CK

INT

CK

EXT

CK

INT

The DLL delays the internal clock (CK

INT

) so that

Delay

DLL

+ D

D

Additional delaythrough DQ drivers

READ

These two edgesnow more closely aligned

CK Buffers

CK Buffers

Delay

DLL

the total delay equals one full clock cycle, and thusCK

INT

is now in sync with CK

EXT

… thus, DQ

EXT

is also (roughly) in sync with CK

EXT

Delay introduced by DLL

CK

EXT

CK

INT

CMD

DQ

EXT

CK

EXT

CK

INT

CMD

DQ

EXT

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!K


!"#$%&'($&%"#)*+,-

!"#"$%&!"#"$'(#

)*'+&#$,- )*'+&#$.-

/012

!"#$%&'%%'($)*'$+,- .

/

0

!"#$%&'11+"

23(45'$6)&+47#$'%&

8+4+'9+"

!+"&'$#1("

3$4'(5#'&$%6677$8999$6+:&"5+&:$;(#'0+"5

./"01'&*-$++,12"3&456,*"6'+'"'*"4711,&+895(+'%,"(,9,("

:/"01'&*-$**$5&";$&,2"<,($9,1"6'+'"=15-"+1'&*-$++,1"+5"

>/"?,4,$9,12"@5-A'1,"'%'$&*+"1,=,1,&4,"+5",B+1'4+"6'+'

C/"0,1-$&'+512"?,-59,"*$%&'("=15-"($&,D"5&4,"+E,)F1,"

5&+5"+E,"($&,

1,4,$9,1

1,4,$9,6G/"@(54H2"0,((*"+1'&*-$++,1"IE,&"+5"*,&6D"1,4,$9,1"IE,&"

+5"*'-A(,"*$%&'(


System Timing

Bruce Jacob


ECE Dept.

SLIDE 7


Idea: Detect “0” vs. “1”

This is a “1”

D Q

Clock

DataD Q

t

bit

V

0

V

1

This is a “0”t

bit

V

0

V

1

EYE: spacet

eye

V

0

V

1

between 1 & 0V

eye


System Timing

Bruce Jacob


ECE Dept.

SLIDE 8


Basic Problem: Voltage Noise

Voltage noise reduces operating margins

t

eye

V

eye

Data signal with

Clock signal with

voltage noise

voltage noise

D Q

Clock

DataD Q


System Timing

Bruce Jacob


ECE Dept.

SLIDE 9


Basic Problem: Timing Noise

Timing noise reduces operating frequency

t

eye

V

eye

D Q

Clock

DataD Q

Clock signal with timing noise

Data signal with timing noise


System Timing

Bruce Jacob


ECE Dept.

SLIDE 10


Basic Problem: Both

Note: Clock signal is just another signal subject to same constraints of voltage noise, skew and jitter as data signals

D Q

Clock

DataD Q

Clock signal with both noise sources

Data signal with both noise sources

t

eye

V

eye


System Timing

Bruce Jacob


ECE Dept.

SLIDE 11


Eye Diagram

Yes, there really is that much voltage noise; Yes, there really is that much timing noise …

Life sucks; deal with it.


System Timing

Bruce Jacob


ECE Dept.

SLIDE 64


Dual Edge Clocking

- Both edges of clock used to latch in data

Data

Clock

- Duty cycle & rise/fall times of clock must be even- Clock signal must be phase shifted by 90 degrees

Data

Clock

- Only one edge of clock latches data- Duty cycle of clock signal is not relevent

relative to phase of data signal

- Clock signal operating at 2X switching rate of data

- How do you get 90 degrees ??

- Always a clock edge where you need one


System Timing

Bruce Jacob


ECE Dept.

SLIDE 14


Cycle Budget

t

cycle

t

eye

t

skew

t

tran

t

skew

= max(skew) + max(jitter) t

tran

= Edge transition time = max(rise_time, fall_time)

t

eye

≤≤≤≤

t

cycle

– t

tran

– t

skew

!"#$%&'())*+),-./!'/01),0

'(.#2$!3456

7'&894:3;<)=1>.)!?

@.>=)!AB=-CDBE#*!FB2$

G2#E).0#1/-H!7.)1)

'<IDJ!58


!"#$%&'()*+,-$&).)"/$012/#3&).)"/$4+5+.#3#56 (77S-=T!'T)U!-2!N.B20,#1!'#*) 544'#S#=-2!-2!N.B20,#1!0#*) 5V444F#.#2$!&!*.#E)!1-!=%#(!(B*V!*.#E)!,-*>S)V!=B.*!W64=,XV!.)=)#E).!,-*>S)V!=%#(!(B*!1-!.)=)#E).:

YV444

'#S#=-2!-2!M)=)#E)!'#*) 5V4447S-=T!'T)U!-2!M)=)#E)!'#*) 5447->(S#2$V!A#11).V!M)HS)=1#-20 Z44[<<!&!<-2$!1).,!\#11). 384&83+, 9:;<=

>48?#5@$7'"*A58"816$B+C#$4)(#,)"#2$D"3#5E+*#$45#6#"3+3)8":$F83*A)(6$GHH


System Timing

Bruce Jacob


ECE Dept.

SLIDE 15


Timing: Clock

∩∩∩∩

Data

Define

when

a value is present on a line …

How many 1’s? How many 0’s?

Need convention to distinguish where one ‘1’ ends and next ‘1’ begins … conventions typically mark boundaries w/

TRANSITIONS

• of the signal itself• of an associated

clock

signal(original definition of “synchronous”)

Uncertainty in timing limits operating speed


System Timing

Bruce Jacob


ECE Dept.

SLIDE 16


Timing Conventions

Apply to both inter-

and

intra-chip signaling


System Timing

Bruce Jacob


ECE Dept.

SLIDE 17


Setup Time

Required time for input to be stableBEFORE CLOCK EDGE


System Timing

Bruce Jacob


ECE Dept.

SLIDE 18


Setup Time Fix


System Timing

Bruce Jacob


ECE Dept.

SLIDE 19


Setup Time Fix II


System Timing

Bruce Jacob


ECE Dept.

SLIDE 20


Hold Time

Required time for input to be stableAFTER CLOCK EDGE


System Timing

Bruce Jacob


ECE Dept.

SLIDE 21


Hold Time Violations


System Timing

Bruce Jacob


ECE Dept.

SLIDE 23


A Tale of Two (or more) Timing Conventions

Synchronous: global clock

Synchronous: source-synchronous I

(“open-loop” meaning no control loop)

Synchronous: source-synchronous II

(“closed loop” meaning feedback control)

Asynchronous: self-timed

Bruce Jacob


System Timing

Bruce Jacob


ECE Dept.

SLIDE 24


System Building Blocks

DELAY ELEMENTS

•

Nominal delay

•

Timing uncertainty, skew, jitter

COMBINATIONAL LOGIC

•

Contamination delay

•

Propagation delay

CLOCKED STORAGE ELEMENTS

•

Align signal to a clock

•

Signal waits to be sampled by clock

•

Output held steady until next clock


System Timing

Bruce Jacob


ECE Dept.

SLIDE 25


Edge-Triggered Register

Samples data on rising edge of CLK

•

Data must remain valid during an

aperture

of time during sampling

Output held steady until next CLK edge

•

Output is held until a

contamination delay

following CLK edge

•

Output has a correct value after a

propagation delay

following CLK edge

TcontaminationTpropagation


System Timing

Bruce Jacob


ECE Dept.

SLIDE 26


Other Storage Elements

LEVEL-SENSITIVE LATCH

•

Passes data through when enable (clock) is high

•

Holds data stable when enable (clock) is low

DUAL-EDGE-TRIGGERED FLIP-FLOP/REGISTER

•

Samples data at both edges of the clock

•

Internally two interleaved flip-flops(1 posedge FF + 1 negedge FF)

•

Allows CLK to run at same speed as data


System Timing

Bruce Jacob


ECE Dept.

SLIDE 27


Eye Diagram, Redux

MAXIMUM OPERATING RATE (i.e., signaling speed)LIMITED BY THREE FACTORS:

•

Tr — Transition time (rise/fall time)

•

Tu — Timing uncertainty, skew, jitter

•

Ta — Aperture time

•

Tbit

≥≥≥≥

Tr + Tu + Ta

(but not that simple …)

t

bit


System Timing

Bruce Jacob


ECE Dept.

SLIDE 28


Synchronous Timing I

GLOBAL CLOCK (Conventional) EXAMPLE

Parameter Symbol Nominal Skew Jitter

Bit Cell (data period)

Tbit 2.5 ns

Transmitter Rise Time

Tr 1.0 ns

Cable Delay

Twire 6.25 ns 100 ps

Receiver Aperture

Ta 300 ps 100 ps 50 ps

Transmitter Delay

500 ps 150 ps 50 ps

Buffer Stage Delay

B# 250 ps 100 ps 50 ps

6.25ns ± 0.1ns8 data linesTx Rx

B1 B4

B1 B4

400MHzMatched Lines ± 0.1ns (1.5cm)


System Timing

Bruce Jacob


ECE Dept.

SLIDE 29



Sources of uncertainty:

•

Skew (across multiple lines) of line delay

•

Jitter of Tx, Rx, and line delay

•

Skew and jitter of global clock (usually large due to high fan-out)

For best performance, center sampling edge on data eye

Gross timing margin = 1/2 [ Tbit - Tr - Ta] = ± 600ps

= 1/2 Tu?


B1 B4

B1 B4


Tbit = 2.5ns

Tbit - Tr = 1.5ns

Ta = 300psMargin = 600ps


System Timing

Bruce Jacob


ECE Dept.

SLIDE 30


An Aside …

Why do we simply add up the uncertainties?And why does each effectively count twice?

DATA w/ no skew/jitter

CLOCK w/ no skew/jitter

DATA

early

by 1 time unit

CLOCK

late

by 1 time unit

1 time unit1 time unit

2 time units


System Timing

Bruce Jacob


ECE Dept.

SLIDE 31



TIMING ANALYSIS

Clock Skew: 100ps lines + 100ps B1 + 400ps B4

Clock Jitter: 50ps B1 + 200ps B4[CLKs times 2: one for xmit, one for recv]

Transmitter: 150ps skew, 50ps jitter

Receiver: 100ps skew, 50ps jitter

Data Cable: 100ps skew

TOTAL: 1550ps skew, 600ps jitter (BAD)


B1 B4

B1 B4



System Timing

Bruce Jacob


ECE Dept.

SLIDE 32



LIMITS TO LINE DELAY & DATA FREQUENCY

Conventional Wisdom: Line Delay Must Be ODD NUMBER of HALF-BITS … WHY?

For fixed line length and tight margins, this limits the bus speeds that can be used


B1 B4

B1 B4


0half-bits

1 2 3 4 5 6 7 8


System Timing

Bruce Jacob


ECE Dept.

SLIDE 33



SUMMARY

GLOBALLY SYNCHRONOUS DESIGN:

•

For long wires and high speeds, only a handful of frequencies work

•

Impractical to control uncertainties

•

Cannot switch frequencies


B1 B4

B1 B4



System Timing

Bruce Jacob


ECE Dept.

SLIDE 34


Synchronous Timing II

PIPELINED TIMING: BASIC IDEA

Delay the clock by the same amount as data … PLUS half a bit-cell

System will work from DC to maximum theoretical frequency 1/(Tr + Tu + Ta)

Defines new clock domain at receiving end


System Timing

Bruce Jacob


ECE Dept.

SLIDE 35



SOURCES OF UNCERTAINTY

SKEW:

•

Between CLK & Data line

•

Fixed differences in FF, Tx, Rx delays

•

Different CLK delays to different FFs

•

Aperture offset in Rx FF

•

Extra offset in the delayed CLK line

JITTER:

•

In Tx clock

•

In FF, Tx, Rx delays


System Timing

Bruce Jacob


ECE Dept.

SLIDE 36



OPEN-LOOP PIPELINED EXAMPLE

6.25ns ± 0.1nsRClk

Tx Rx

B1 B4

200MHz

6.25ns ± 0.1ns8 data linesData In

Toggle

Sync

90°

B1Lines need notbe matched

B4

Internal Clock Network


System Timing

Bruce Jacob


ECE Dept.

SLIDE 37



TIMING ANALYSIS

Xmit data: 150ps skew, 50ps jitter

Xmit toggle: 150ps skew, 50ps jitter

Receiver: 100ps skew, 50ps jitter

Data cable: 100ps skew

Toggle clock cable: 100ps skew

TOTAL: 600ps skew, 150ps jitter (BETTER)

6.25ns ± 0.1nsRClk

Tx Rx

B1 B4

200MHz


Toggle

Sync

90°


B4



System Timing

Bruce Jacob


ECE Dept.

SLIDE 38


Synchronous Timing III

CLOSED-LOOP PIPELINED EXAMPLE

Variable delay line can cancel ALL SKEW

6.25ns ± 0.1nsRClk

Tx Rx

B1 B4

B1

200MHzLines need not


Toggle

be matchedB4

FSM

90˚

Sync

To rest of receive chip

Bruce Jacob

(almost)

Bruce Jacob

^


System Timing

Bruce Jacob


ECE Dept.

SLIDE 39



COMPONENTS of CONTROL LOOP (DLL)

Rx

FSM

90˚

Sync

PhaseCompare

LoopFilter

VariableRef.Clock

Ref.Data/CK

DelayedClock(Output)

delay line

(Input)

(Input)

(control)

D QB

A

Y

Y

PHASE

AB

0˚ 90˚ 180˚ 270˚ 360˚

DFF as a Phase Comparator


System Timing

Bruce Jacob


ECE Dept.

SLIDE 40



TIMING ANALYSIS

Xmit data: 50ps jitter

Recv data: 50ps jitter

Xmit toggle: 30ps skew data/toggle (0?), 50ps jitter

Recv toggle: 20ps skew (0?), 50ps jitter

Data cable: 100ps skew

Toggle clock cable: 100ps skew

TOTAL: 250ps skew, 200ps jitter (GOOD!)

6.25ns ± 0.1nsRClk

Tx Rx

B1 B4

B1



Toggle

be matchedB4

FSM

90˚

Sync



System Timing

Bruce Jacob


ECE Dept.

SLIDE 41


Synchronous Timing II & III

LIMITS TO LINE DELAY & DATA FREQUENCY

None.

Only limiter to bus frequency is the rate at which you can successfully transmit & receive data (e.g. Taperture + Tuncertainty + Ttransmit)

6.25ns ± 0.1nsRClk

Tx Rx

B1 B4

B1



Toggle

be matchedB4

FSM

90˚

Sync


6.25ns ± 0.1nsRClk

Tx Rx

B1 B4

200MHz


Toggle

Sync

90°


B4


CK

Clock domains: CK DQS

Memory Controller

DRAM A DRAM B DRAM C

Time

CMD

DATA A

DATA B

DATA C

Data from A:

Data from B:

Data from C:

Delay through each DRAM equals quarter of an hour on clock

CMD Bus

DATA Bus

Bruce Jacob

Example from the other day (re: question — why doesDDR need a turnaround time but Rambus does not?)

Documents

3456 3; &./0(+/1%blj/CS-590.26/lectures/LectureG.pdf · 0 3456 3;? c 2$ 1/) 3 kd 953a+b=9.89!" &!’ & * & 9 < =;"> =*?> =;@> =;’> =;a> =*a> i-/, i =*k>

3456 3; &./0(+/1%blj/CS-590.26/lectures/LectureG.pdf · 0 3456 3;? c 2$ 1/) 3 kd 953a+b=9.89!" &!’ & * & 9 < =;"> =?> =;@> =;’> =;a> =a> i-/, i =*k>