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ELSEVIER Microelectronic Engineering 36 (1997) 395-398

MICROEI,ECTIONIC ENGINEERING

D e t a i l e d character izat ion o f U n i b o n d mater ia l

D. Munteanu, a C. Maleville, b S. Cristoloveanu, a H. Moriceau, b B. Aspar, b C. Raynaud, e O. Faynot, e J-L. Pelloie, c A-J. Auberton-Herv@ d

aLab. de Physique des Composants h Semiconducteurs (UMR CNRS & INPG) ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France

bLETI-CEA/DMITEC, 17 rue des Martyrs, F38054 Grenoble Cedex 9, France

eLETI-CEA/DMEL, 17 rue des Martyrs, F38054 Grenoble Cedex 9, France

dSOITEC, Site ASTEC, B.P. 85X, 38041 Grenoble Cedex, France

Unibond wafers are evaluated by optical, physical (TEM, AFM, X-ray), chemical (Secco and HF etch), and electrical (ko-MOSFET, Hall, p-PCD) methods. The low density of defects, the high quality of oxide and interfaces, and the excellent electrical properties (carrier mobility and lifetime) are key properties. The parameters extracted from MOS test devices confirm that Unibond is a very suitable technology for thin-film CMOS circuits.

1. I N T R O D U C T I O N

Silicon On Insulator (SOI) is certainly the most suitable technology for the fabrication of low- voltage/low-power integrated circuits [1]. The SOI potential will be materialized only if sev- eral practical conditions are fulfilled: wide avail- ability, high quality, and reasonable cost of SOI wafers. These constraints can be met by the novel Unibond material, which is formed with the Smart-Cut process discovered by Bruel [2].

In this paper, we present a comprehensive and extensive study of the relevant properties of Uni- bond wafers. Our investigations were conducted., at the wafer level or on fully-processed MOS tran- sistors, by using a set of physical, chemical, and electrical characterization techniques.

2. W A F E R F A B R I C A T I O N

State-of-the-art Unibond is synthesized with a ba- sic four-step process: (i) deep hydrogen implanta- tion into an oxidized Si wafer A, (ii) hydrophilic bonding of wafer A to a wafer B, (iii) annealing

which increases the bonding strength and causes the separation of wafer A at the boundary defined by hydrogen-induced microcavities, and (iv) fine polishing to erase the roughness of the Si film.

The advantages of Unibond over standard Wafer Bonding materials come from the simpler and more economical processing sequence: (i) it is a one-wafer-process because wafer A can be recy- cled as a subsequent wafer B, and (ii) it avoids the critical etch-back step. As compared to SIMOX, there are also several key benefits: (i) commer- cially available hydrogen implanters (unlike the case of sophisticated oxygen implanters), (ii) flex- ible geometry, in terms of thicknesses of the sil- icon film and buried oxide, achieved by adjust- ing the implant energy and oxidation time, (iii) shorter times needed for implantation, therefore higher throughput, (iv) thermal oxide interface between Si film and BOX (the bonded interface being located underneath the BOX), etc.

Our investigation is focused on Unibond wa- fers with 200 nm thick Si-film and 400 nm thick oxide (Fig. 1). This geometry mimics that of standard SIMOX and allows a direct comparison,

0167-9317/97/$17.00 © Elsevier Science B.V. All rights reserved. PIh S0167-9317(97)00088-9

396 D. Munteanu et al./Microelectronic Engineering 36 (1997) 395-398

Figure 1. TEM cross-section of Unibond. Figure 2. Surface roughness by AFM in a 4" Unibond wafer (1 × 1 #m 2 scan area, typical RMS: 0.13rim).

2. W A F E R C H A R A C T E R I Z A T I O N

2.1. P h y s i c a l a n d s t r u c t u r a l p r o p e r t i e s

The use of a thermal oxide as the buried layer achieves a very good insulation integrity. Thick- ness uniformity of the BOX is routinely better than ±3 nm. By comparison with SIMOX wafers, where pipe density could be above 0.1 cm -2, nei- ther pipe nor silicon island is evidenced in Uni- bond oxides [3]. Since the bonding interface is the deepest one, the defect densities at the top inter- face are lower than in low-dose SIMOX wafers. Moreover, thermal treatments are done in the Smart-Cut process at lower temperatures than for SIMOX. It results a lower density of interstitial silicon inside the Si film, leading to reduced con- centrations of crystalline defects.

All these defects are evidenced by chemical etching and either optical or SEM observations. HF etching is used to reveal any defects, thread- ing the top silicon layer. Typical density val- ues are less than l c m -2. In parallel, Secco so- lution allows to enhance crystalline defects in the top silicon layer via a selective etching. When only 50 nm thick Si overlay is left, defect densi- ties are in the 103-104 cm -2 range. By contrast to the case of SIMOX, synchrotron X-ray analysis shows a very low density of threading dislocations (< 30cm -2) on Unibond structures [3].

Because of the surface roughness after the

thermal splitting, it is necessary to use a touch polishing step. So, despite of the good control of the thickness allowed by the implantation pro- cess, the final thickness uniformity and surface roughness are mainly dependent of the polishing parameters. The fine control of the polishing step allows thickness uniformity better than ± 5 n m over 4", 6" or 8" Unibond wafers. Measured RMS values are as low as 0.13nm (Fig. 2) and PSD values are used to characterize the surface micro- roughness over 1 × 1 #m 2 and 50 × 50 #m 2 scans. The roughness achievable is comparable to that of prime quality bulk-Si wafers and so, is compatible with wafer requirements for ULSI. Finally, TEM observations are used in the cross section mode to check the high quality of the Unibond structure (Fig. 1). After removal of the Si film, using a se- lective etching, the microroughness of the buried oxide layer is 0.14nm RMS; we correlate the car- rier mobility and oxide roughness values.

2.2. Electrical propert ies

Pseudo-MOS transistor (~/-MOSFET) and Hall effect measurements demonstrate that the elec- trical properties of as-grown Unibond wafers are equally promising. The residual doping is p-type (as in the original Si wafer) with a concentration below 5 x 1015 cm -3. Spreading resistance profil- ing, performed at the surface region of control Si

D. Munteanu et al./Microelectronic Engineering 36 (1997) 395-398 397

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Figure 3. Carrier lifetime measured by microwave photoconductive decay (mean value in the Si sub- strate: 42/ts, for 8" Unibond wafers).

wafers implanted with hydrogen, confirm that hy- drogen completely diffuses away from the Si wafer during high temperature annealing, leaving the electrical properties of the crystal unchanged [4]. The Unibond film has in-depth homogeneity with high carrier mobilities. At the film-oxide inter- face, the electron and hole mobilities (/tn ~- 650- 700em2/Vs, #p _ 250cm2/Vs) are among the best measured in SOI.

The density of traps at the upper interface of the BOX is below the detection limit of 3 x 1011 eV - 1 cm- 2, in other words the interface qu al- ity was not degraded by hydrogen implantation or thermal annealing. The carrier lifetime was eval- uated by photo-conductivity decay in the Si sub- strate (Fig. 3) and transient ~-MOSFET tech- nique (Fig. 4) [5]. The generation lifetime in the Si film may exceed 100#s in Unibond and out- performs the value measured in SIMOX.

3. D E V I C E C H A R A C T E R I Z A T I O N

A variety of transistors and test devices were fabricated with standard CMOS/SOI process [6]. The final thicknesses of the Si film, gate oxide and buried oxide are, respectively, 180nm, 7 nm, and 400nm. The film doping is 3 × 1017cm -3 at the front channel and 7 x 1017cm -3 at the back chan- nel; the transistors operate in partial depletion

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5 10 I I

15 20 25 30 I L I

UNIBOND

SIMOX

VG : 0 ---) -20 V

V D = 100 mV

I I I I 100 200 300 400 500

Time (s)

Figure 4. ~-MOSFET drain current transients giv- ing the carrier generation lifetime in the silicon film of Unibond (100 #s) and SIMOX (10/zs) wafers.

mode. Thorough characterization was performed to compare the properties of the front and back channels in terms of threshold voltage, transcon- ductance, subthreshold swing, and leakage.

The threshold voltages meet the target val- ues, 0.7V for the front channel and 65V for the back channel (Fig. 5), expected from the implant conditions. This indicates the absence of any par- asitic source of residual doping (film contamina- tion, hydrogen activation, etc). The front chan- nel subthreshold swing is 80mV/decade which reflects the normal quality of the gate oxide in- terface (Dit < 3 x 101°eV-lcm-2). The back channel swing, 2.4V/decade, is governed by the buried oxide capacitance. The density of traps at the upper interface of the BOX remains small, confirming that the 'thermal oxide' nature of this interface has not been damaged by the process.

The field effect mobility of electrons, extracted from the linear ID/v"f~m(Va) plot and from the transconductance peak, is 350 cm2/Vs in edge- less, long channels, which is normal again when referred to the high film doping. The back chan- nel mobility is slightly smaller (250-320 cm2/Vs) due to the retrograde doping profile. The tran- sistor edges may operate in full depletion mode with high carrier mobilities.

The carrier generation lifetime was measured with a dual gate transient technique [7]. The front gate is biased in inversion whereas the back gate is pulsed into accumulation (Fig. 6). The resulting transient of the drain current was an-

398 D. Munteanu et al./Microelectronic Engineering 36 (1997) 395-398

160 140 (gm)max = 4.2 g S

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1oo- / ,, / 8 o -

I / / ~ 40- / / /

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0 20 40 60 80 Back gate voltage VG2 (V)

10-03 16

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100

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Figure 5. Back-channel current (--) and transcon- ductance (- - -) in a partially depleted, edgeless, n- channel Unibond MOSFET (L = 2 #m, W = 40 #m).

- ~ with lamp illumination, VGI = 3V

~ ' - ~ dark, Vct= 3V

_• VGl = 2V

VG2 ---- 0 -'~ -30 V

I I I I 100 200 300 400

Time (s) 500

Figure 6. Dual-gate drain current transients in a partially depleted Unibond n-MOSFET, for various front-gate voltages.

alyzed with a Zerbst-like method, which yields lifetime values between 3-5 #s and very low sur- face generation velocities (0.02cm/s). As com- pared to recent data on SIMOX transistors [8,9], the lifetime appears to be one order of magnitude higher in Unibond. Furthermore, the difference in carrier lifetimes, extracted from ~-MOSFET or MOSFET transients, indicates a reasonable life- time decrease during the device processing (due, mainly, to a much higher doping level), but no apparent degradation of the trap density.

4. C O N C L U S I O N

Several characterization methods, conceived for SOI or imported from bulk silicon, have been used to reveal the prominent properties of Uni- bond structures. The silicon film is device-grade, wafer-scale monocrystal with high quality and ex- cellent electrical properties. The buried oxide and its upper interface have 'thermal' quality. It is concluded that Unibond wafers offer the quality needed for SOI to compete in the arena of main- stream integrated circuits.

Acknowledgements. Thanks are due to Dr. A.M. Papon for TEM analysis. Unibond and Smart-Cut are trade marks from SOITEC Co.

R E F E R E N C E S

1. S. Cristoloveanu and S.S. Li, Electrical Char- acterization of Silicon-On-Insulator Materi- als and Devices, Kluwer, Boston (1995).

2. M. Bruel, Electron. Lett., 31 (1995) 1201. 3. B. Aspar, H. Moriceau and A.J. Auberton,

Electrochem. Soc. Proc., 96-3, (1996) 99. 4. S. Cristoloveanu, A. Ionescu, C. Maleville,

D. Munteanu, M. Gri, B. Aspar, M. Bruel and A.J. Auberton-Hervd, Electrochem. Soc. Proc., 96-3 (1996) 142.

5. A. Ionescu, S. Cristoloveanu, D. Munteanu, T. Elewa and M. Gri, Solid-State Electron., 39 (1996) 1753.

6. J.L. Pelloie, O. Faynot, C. Raynaud, B. Du- nne, F. Martin, S. Tedesco and J. Hartmann, Proc. IEEE Int. SOI Conf. (1996) 118.

7. D. Ioannou, S. Cristoloveanu, M. Mukherjee and B. Mazhari, IEEE Electron Device Lett., 11 (1990) 409.

8. H.C. Shin, I.S. Lim, M. Racanelli, W.M. Huang, J. Foerstner and B.Y. tIwang, IEEE Trans. Electron Devices, 43 (1996) 318.

9. S. Cristoloveanu, A. Ionescu, T. Wetteroth, It. Shin, D. Munteanu, P. Gentil, S. Hong and S. Wilson, J. Electrochem. Soc. (1996).