Epitaxial silicon chemical vapor deposition below atmospheric pressure

Materials Science and Engineering, B4 ( 1989) 407-415 407

Epitaxial Silicon Chemical Vapor Deposition Below Atmospheric Pressure

J. L. REGOLINI and D. BENSAHEL

Centre National d'Etudes des Tdl~;comrnunications, BP 98, 38243 Meylan (France)

J. MERCIER

Laboratoire d'k/tudes de~ Propri~t~s El~ctroniques des Solides, ('entre ~?aional de la Recherche Scientifique, A v. des MarO'rs, 38040 Grenoble (France)

(Received May 31, 1989)

Abstract

Several investigations have been devoted to silicon epitaxial chemical vapor deposition (CVD) under reduced or low pressure conditions. The aim of these activities is to obtain device quality silicon layers at temperatures well below those generally used in CVD at atmospheric pressure (i.e. above 1000 °C). Kinetic aspects can vary according to the pressure regime. Hence, the reacting gas decomposition, in addition to the by-product formation, is" affected by the total reactor pressure. According to the literature, silicon selectivity can only be obtained by the addition of hydrochloric gas during the reaction. The possibility of selectivity without the addition of this gas is presented. We describe some of the kinetic results as observed in a rapid thermal processing reactor, working at a total pressure of a few 7 orr, where the two systems dichlorosilane and silane both diluted in hydrogen, are presented and discussed. Some of the most recent experimental developments" are schematically described in addition to their most impressive results. The importance of the silicon surface preparation prior to deposition is reviewed, together with the structural defects induced on the epitaxial layer. Doping redistribution is shown as one of the most relevant parameters leading to the low temperature process. Other structural effects such as loading effects or selective epitaxial growth are presented.

1. Introduction

Epitaxial silicon layers are usually grown at a temperature greater than 1000°C which corresponds to the mass transport limited regime. This temperature range is imperative if low defect den-

sities and significant growth rates are required. In this regime the surface diffusion rate is suffi- ciently high, and hydrogen acts as a reducing agent removing any chemical species that could interfere with perfect single crystal formation. Thus, growth rate and crystal perfection can be easily obtained.

With the continued scaling of device structures to the submicrometer level there are two relevant points when using epitaxial structures: ( 1 ) how to minimize the transition region width (autodoping) between the substrate and the epitaxial layer and (2) how to optimize the lateral and vertical isolation between the different active areas.

The immediate answer is to lower the deposition temperature. However, in such a case, adsorbed species such as oxygen, carbon, H20, chlorine and their related compounds interfere with the single crystal growth because of incom- plete desorption. Furthermore, the processing pressure should be reduced to facilitate desorption of impurities. Such considerations have led to new epitaxial processing techniques to achieve low temperature epitaxy in low pressure reactors which are at present under development. This advance is assisted by the progI:ess in vacuum systems, gas and materials purity and availability.

Sharp epitaxial-substrate transition region widths have been obtained at temperatures as low as 550 °C by using for example molecular beam epitaxy (MBE) [1]. In this particular case the system pressure during silicon deposition is in the order of 10 -s Torr. By plasma enhanced chemical vapor deposition (PECVD) at temperatures between 700 and 800°C [2] sharp transitions have also been obtained. In both cases, however, the epi-layer quality is only moderate. The dislocation densities could be as high as 105 cm 2.

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Thus, deposition at reduced pressure improves crystal quality by enhancing the removal of foreign atoms from the surface. As an example, a deposition temperature of more than 1000 °C is required to obtain a low defect density at atmospheric pressure, whereas the equivalent result can be obtained at 800-900 °C when the pressure is lowered to the 50-300 Torr range [3]. Thus, as an approximate criterion, the lower the process temperature, the lower the working pressure has to be to achieve an equivalent crystalline layer quality.

However, low temperatures (below 950°C) also mean low surface mobility for the adatoms to be incorporated into the crystal lattice thus increasing the importance of surface cleanliness before deposition. In this case the adsorbed species can be the rate limiting step as in the case of silane between 600 and 700°C reported by Donahue and Reif [4]. They measured 51 kcal mol-~ for the activation energy, instead of the expected value (about 40 kcal mol-~) for low temperature deposition from chlorosilanes. These observations are in agreement with the theory that, in this case, the rate limiting step is the desorption of hydrogen from the surface which is more important than the reactive desorption of Sill2 molecules.

Concerning the lateral isolation between active elements in an integrated circuit (IC), the local- ized oxidation of silicon (LOCOS) process has certain limitations, such as its scalability limit, and the temperature process which is at about 950 °C for a few hours, leading to oxidation-induced stacking faults (OISF) and dopant redistribution. Thus, one attractive alternative to LOCOS is selective epitaxial growth (SEG) for lateral isolation and epitaxial lateral overgrowth (ELO) for vertical isolation [5, 6]. These two techniques will be discussed later in detail.

In fact, several types of silicon epitaxial reactors, called "unconventional" reactors have been developed during the past ten years and according to the literature they are today producing high quality/low temperature silicon epitaxy. To achieve low temperature CVD, two types of systems are emerging. Meyerson [7] has developed an ultra low pressure CVD (ULPCVD) technique using a multi-wafer, hot-wall reactor working between 600 and 900 °C in the mTorr working pressure regime. Gibbons et al. [8] have con- structed a single wafer cold wall CVD system based on a rapid thermal processing (RTP) sys-

tem where the reacting and carrier gas flux ale: established and the temperature is used a~s a "switch" to turn on and off the reaction in the Torr pressure range. Similar systems have also been adopted by other laboratories 19, l{t!. Epitaxy requires a cleaning step, and low temperature surface cleaning is not an easy task; nor is dopant incorporation when the thermal energy is not high enough. For this reason certain laboratories have developed assisted CVC such as PECVD [2, 11] or UVECVD [121 for I IV enhancement. Each of these techniques has nucleated certain kinds of "schools" with different interests, results and drawbacks that we will try to analyze from the point of view of system versatil- ity and epitaxial silicon layer quality.

The most representative system working in the low (reduced) pressure/low (reduced) temperature regime will schematically be described, and the most relevant results will then be presented and compared. However, even though silicon MBE has been carefully investigated and high quality films have been grown [ 13 ] some compari- sons with other methods will be made. However, a more extensive analysis of this particular technique is not within the scope of the present review.

As a final remark, we note that since these techniques are new, only a small amount of work has been devoted to the fabrication of complex circuits. All the published results concerning minority carrier lifetime, mobility, ew. cannot be reviewed because they are spread out and finally, they are depending on the complete fabrication process. Most of the published work is material characterization oriented.

2. Experimental details

The use of a background pressure of 10 ~' Torr is necessary to maintain a partial pressure lower than 10 -s Torr of both 02 and H20 to obtain an oxide-free silicon surface. In addition the deposition pressure of about 1 mTorr is crucial; if the gas source has 10 ppm H20, its partial pressure will be below 10 -s Torr, i.e. not exceeding the limiting partial pressure for stable oxide formation. This is the approach of Meyer- son and his group at IBM [7]. For this reason a load-lock ultrahigh vacuum system is used with a multiwafer hot-wall reactor. Deposition of epitaxial silicon is achieved at a temperature between 550 and 850 °C using 2 sccm (standard

cubic centimeter per minute) of silane and 20 sccm of hydrogen in 120 rain cycles to form about 0.5 ,urn.

The aim of these low temperature methods is to reduce the "diffusion distance" of dopants, Dt (where D is the solid state diffusion coefficient and t is the time), at values compatible with today's high performance ICs [14]. However, even at high temperature, a rapid processing may be included in the category of "low temperature process" and this is another approach pioneered by Gibbons et al. [8]. According to this group, diffusion and ion implantation are the two commonly used methods for doping semiconductors. In very large scale integration (VLSI), however, where abrupt doping transitions and ultrathin, heavily doped layers are required, these techniques may be beyond their capabilities. Thus, a technology with the interface control of MBE and the doping range of CVD can be provided by limited reaction processing (LRP). This system consists of a radiantly heated reactor, with no inertia (300 °C s-~) where the temperature is used as a "switch" to turn the CVD reaction on and off. The substrate is only hot while the deposition or surface reaction is occurring, not during purging, gas flow stabilization and other process modes. This minimizes diffusion and intermixing [15].

We adopted a similar set-up based in a hori- zontal cold-wall air-cooled silica chamber where the back of the wafer is heated directly by air- cooled tungsten lamps [10]. The pumping system, which is only a mechanical roughening pump, gives a background pressure of 2 mTorr. A permanent flux of hydrogen is used as a purging and carrier gas after evacuating the system. Such a flow minimizes contamination during the complete process and the temperature cycles, which are between 650 and 1100 °C, are 2 min long at most. A similar system was also adopted by Green et al. [9] at Bell Laboratories where they included an oil-free pumping stage reaching a base pressure of 10-7 Tort in a cylindrical metallic reactor. The single wafer is heated through silica windows by two tungsten-halogen lamp banks.

If the low temperature process can minimize the diffusion length for ultrathin structures, it can, however, create at least two other problems: (1) the "in situ" removing of the native oxide prior to deposition and (2) the migration of adatoms adsorbed at the surface for incorporation in the energetically favorable sites in the crystal lattice.

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To solve these problems, the effect of ion bombardment on film growth has been investigated [2]. An r.f. plasma is added to a cold-wall reactor where a single wafer is radiantly heated. This plasma-enhanced CVD has three major effects: (a) the sputtering of contaminants at the sample surface, such as native oxide or others, (b) the enhancement of the adatom surface mobility, which is very important for some types of dopants and (c) the creation of adsorption sites. All these effects could be beneficial for a low temperature (LT) process, mainly for the cleaning step before deposition.

Several RTP systems are commercially avail- able for use as a CVD reactor. More currently used are the radiantly heated systems for multiwafer processing working in the pressure range between 10 and 100 Tort and temperatures below 1000 °C. These systems will be referred to as the cold-wall, barrel reactors and as far as we know they are the only ones used, at present, in industrial applications.

3. Kinetics

Epitaxial growth occurs by heterogeneous composition of silicon compounds brought as gas to the substrate surface. Thus, adsorption, reactive desorption and surface diffusion are all ther- mally activated. It has been shown that reduced pressure and reduced temperature, once the diffi- culty of surface preclean is overcome, should lead to high quality films which are even better than conventional high temperature films [14].

3.1. A tmospher i c pressure Kinetic studies have been carried out at atmos-

pheric pressure by Bloem and Claassen [16, 17], Stassimos et al. [18] and others. They concluded that no matter what the starting material is, i.e. whether it is Sill4, SiH2C12 or SiCl4, the same growth mechanism is operative owing to the similar chemical nature of these compounds and the reactions involved in H~ and/or HC1. The proposed adspecies responsible for the silicon growth are Sill 2 and SiC12. From this point of view, they explain the growth behavior of silicon from SiHJHCI/H 2 and prove that the role of HC1 is the etching of silicon, its major role being the determination of the relative amounts of Sill, and SiC12. For dichlorosilane (DCS), the proposed decomposition is SiH2C12 ~ SiC12 + H 2 and the equilibrium conversion is S i C L + 2 H ~

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SiH2+2HC1. Thus from that point of view, DSC/H 2 and SiH4/HCI/H 2 are completely equivalent systems.

Therefore, the adsorption and subsequent surface reactions, leading to silicon growth due to the adspecies Sill 2 and SiC12 are

Sill 2 + * ~ SiH~*

Sill2* ~ Si + H, (1)

SiC12 + * ~ SIC12*

SiCl2* + H, *-, Si + 2HC1 (2)

where * represents a crystal site and the reverse path of reaction (2) corresponds to silicon etching. In eqn. (2) a quadratic dependence of the growth rate (G) on the HC1 partial pressure is proposed.

Concerning the apparent activation energy (E~,) obtained using silane diluted in H2 at atmospheric pressure, Beers and Bloem [19] obtained a value of between 32 and 38 kcal mol -~ in the 650-850°C temperature range, which is interpreted as surface-controlled growth rate. Below this temperature range, E~ = 51 kcal mol-~ and the regime is also surface controlled, but in this region, G is limited by the desorption rate of the hydrogenated substrate surface. Above 850°C the Gvalues are limited by the gas phase diffusion of the reactants toward the solid surface.

3.2. Reduced and low pressure Duchemin et al. [20], also using silane diluted

in H 2 at pressures between 10 and 500 Tort, obtained about 15 kcal mol - ' for E~ at 10 Torr in the 750-1050°C temperature range and (111) oriented substrates. They interpreted these results as a reaction-controlled growth rate. Moving to a pressure of about 70 Torr there appears to be a temperature region (above 850 °C) where G is limited by the gaseous diffusion. The same behavior is also obtained at 500 Torr and the growth rate is insensitive to temperature. Hottier and Cadoret [21] have obtained about 10 kcal mol-~ at 10 Torr concluding that the reaction is a kinetic process limited by surface diffusion of silane molecules inhibited by adsorbed hydrogen.

The growth rate of epitaxial silicon films, deposited with and without plasma enhancement from a silane source, has been studied by Donahue and Reif [2]. They found 13 kcal mol- for E~ throughout the investigated temperature

range (600-800 °C)when rising plasma cnimncc ment. When no plasma wa~ used, they obtained the following values for f i ' S kcal tool * for ~em peratures between 6511 and 81!t) °C, and about 5i~ kcal mol ~ for temperatures below 7011 °C. This change below 700°C reflects the !act that the decomposition of silanc w the dcsorption ot hydrogen has become the rate limiting step, h shows also that the plasma growth mechanism is only weakly sensitive to surface characteristics.

In our case we have reported !22! t~ = 38 kcal tool ' below 800 °C at 2 Ton using sihmc and 59 kcal mol ~ when using DCS. The first value com- pares quite well with that obtained by Beers and Bloem [19] at atmospheric pressure, l~or the second one, the reported values range between 40 and 50 kcal tool ~ [23, 24 and we obtained a value of about 60 kcal mo] ~ This result has led us to propose another model for the DCS/H2 system different from the well-accepted SiHzCI~-- SiCI z +H, . It has been reported by, Ho and Breiland [25] that the DCS decomposition at low pressure follows SiH,CI., -~ SiHC1 + HC1. Taking this result into account and also the dissociation energy of the DCS molecule published by lshitani et al. [26] as being 61 kcal tool ~, we propose a rate limiting reaction which results [27] in a linear dependence of G as a function of the HCI partial pressure and no dependence on the H e partial pressure. These results arc in agreement with the experimental observations and also explain ~he selectivity obtained with no addition of HC1 as will be reported below.

4. Surface preparation

Surface preparation, prior to epitaxial growth, is clearly the most crucial point in obtaining high quality, VLSI compatible, single crystal layers whatever growth temperature and pressure are used. Two steps are generally applied: (i) one out- side the reactor, by using well-known chemical procedures such as published by Kern and Puotinen [28] or lshizaka and Shiraki [29] and (ii) the second, an "in situ" cleaning which can vary considerably according to different laboratories.

For the "in situ" process, the reduced pressure contributes to the removal of most of the adsorbed impurities or native oxide. For example, at 760 Torr, in H2, the native oxide can be removed at 1150 °C in a few minutes. By decreasing the pressure to 25 Torr, the temperature can be lowered to 950°C and even further at still

lower pressures. However, several minutes are required which, in some cases, may not be compatible with the whole process.

According to Srinivasan and Meyerson [14], to maintain an oxide-free surface with about 10 2 Torr of 02, a temperature of above 1100 °C is required. At 850 °C this partial pressure should not exceed 10 5 Tort. Also carbon contamination can nucleate 02 or H2O present in the carrier gas such as H 2. Thus, temperatures in excess of 1000 °C are required prior to the deposition step. A good strategy could be a high temperature (HT) prebake followed by a low temperature (LT) epitaxial growth. This is called the H/LT process which could give an even lower defect density than there is in the substrate material [14].

In the RTP systems, the "in situ" sample cleaning at temperatures above 1000 °C needs a few seconds in a H 2 or H2/HCI gas mixture [8-10] with satisfactory results.

For an LT "in situ" cleaning procedure Burger and Reif [30] developed an argon plasma assisted method limited to 800 °C, which gives essentially dislocation-free epi-silicon layers at that temperature. The possible damage created during ion bombardment is minimized to few monolayers and is continuously self-annealed during the ion sputtering with the flux, dose and ion energy carefully controlled. A similar method, but at a still lower temperature and ion energy, has been presented by Ohmi et al. [31] and by Burke and Pomot [ 11 ].

At this low temperature, under hydrogen flux and deep UV radiation, we obtained satisfactory results on samples previously chemically cleaned or as received [10].

Systematic investigations concerning surface precleaning are carried out permanently, the initial surface being vital to the overall achieve- ment of LT epitaxy.

5. Residual defects

We include in this section some of the most common structural defects, such as dislocations or stacking faults (SF) induced by insufficient surface cleaning or contamination during epitaxial growth. Other types of defects such as faceting or loading effect will be treated separately.

Transmission electron microscopy (TEM) together with chemical decoration are the most adequate techniques for characterization and counting of structural defects.

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Using the UHVCVD technique, Meyerson [7] has observed a critical transition temperature, between 750 and 800 °C where the defect density may range from 10 s cm 2 to nearly "defect free" material with 103 cm 2. These defects, as observed by TEM, are pinholes extending to the substrate. They are related to non-standard operation and non-cleanroom environments. Because of a UHV system used by Meyerson [7] carbon and oxygen in the epitaxial layers are below secondary ion mass spectroscopy (SIMS) background. From the device point of view, the most important defects are the electrically active ones and even if dislocations or SF are not electrically active, they can act as a getter for metals or other contaminants and become leakage paths.

This transition temperature has also been observed by Drowley and Turner [23] in a commercial reduced pressure reactor at around 850°C. The films exhibited practically "no defects" after chemical decoration, although, below 800 °C a high density of SF appeared.

As pointed out by Gibbons et al. [32], the LRP has two inherently potential problems for the growth of more than one layer: (i) non-optimum deposition during the thermal transients and (ii) contamination at the interupted growth interface. As previously reported [9, 33, 34], the first interface (between the substrate and the first layer) could have some precipitates or residues left by insufficient cleaning, as observed by cross- sectional TEM. These defects can disappear when a complete "ex situ" chemical treatment is followed by an "in situ" high temperature cleaning prior to deposition [34]. The thin line also present at the first interface (when growing two or more successive layers)is different in nature. For example, during the initial thermal transient, the reactive gases are flowing and some amorphous or polycrystalline material may be deposited, potentially nucleating defects on the substrate. In this case these interfaces should be more evident or larger when using a higher reactive gas flow but we observed just the opposite. With increasing silane flow, these interfaces disappear within the resolution of cross-sectional TEM. Thus our interpretation is mainly consistent with surface contamination occurring during the cooling down time after each cleaning or deposition step. During this time the silicon surface can getter impurities (02 or H20) from the carrier gas flow. If the deposition temperature as well as the silane flow are increased interfaces are no longer

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observed indicating that desorption from the surface and/or silane reduction are the cleaning mechanism.

These cross-sectional TEM studies were com- pleted by carrier concentration measurements from C - V curves obtained in Schottky diodes over multilayer samples. In addition by deep level transient spectroscopy we obtained the corresponding carrier trap density for these interfaces with about 5 x 10 ~3 cm -3 as a maximum value [34], the best reported values being 10 II cm-3 [32].

High carbon contamination has been observed in an RTP system where the epitaxial growth cycle is about 15 rain [9]. This long process for a "rapid" system can induce reactor outgassing (gasket seals) giving a high contamination level.

In an LRP system [15] the obtained defect density is less than 10 cm 2 when using p+ substrates and about 3000 cm-2 in n substrates, sug- gesting some internal gettering mechanism. What is more relevant is that a low defect density is obtained in a system without a cleanroom envi- ronment or an ultrahigh vacuum pumping system. In ref. 15 a permanent hydrogen flow is used as a purging and carrying gas, and in addition the carbon and oxygen contamination is very low, below 1017 and 5 x 1017 cm -3, respectively.

In a system using PECVD, where the presence of oxygen and carbon is quite high [2], more than 102o and 1018 cm -3, respectively, and indepen- dently of the growth temperature, the impurities induce nucleation resulting in SF or saucer-pits- type defects. In all cases, by optimization of the "in situ" cleaning procedure and with low r.f. power (5 W), low susceptor bias (100 V)it is possible to grow epitaxial films at 750 °C with about 10 dislocations cm 2 in about 20 min. However, precipitates related to oxygen and carbon impurities are always present at the interface.

At temperatures higher than 800 °C, dislocations and SF can be minimized. What still remains is carbon, oxygen and metallic impurities that could have an effect on the electrical characteristics thus affecting the adatom surface moNlity and facilitating the incorporation of point defects.

6. Doping redistribution

Autodoping is an unintentional dopant incorporation into the epitaxial layer and comes from the heavily doped substrate during the process

which can result in an unwanted doped epi-layc~. This autodoping appears vertically and laterally. The former occurs as a combination of both solid state diffusion from the doped buried layer int~ the epi-layer region directly above and also from gas phase transport. The lateral autodoping is produced by the dopant evaporation at the substrate surface resulting in a redistribution and partial transfer into the adjacent substrate areas. The latter is particularly difficult to control because it depends on many experimental conditions such as gas flow. ett.

Solid state outdiffusion may be minimized for all dopant species using a relatively low epitaxial growth temperature (850 °C). It should, however, be noted that different dopant species (boron, phosphorus, arsenic, antimony) tend to behave differently with respect to expitaxial growth parameters concerning the autodoping.

I~br example, at 1050 °C and atmospheric pressure (AP) if the boron level in the obtained epi- layer is 4 x 10 ~4 cm-~, the same experiment at reduced pressure (RP) of 28 Torr gives 2 x 1015 cm ~. At this RP, and 800 °C, the value is less than 1014 cm -3 [5]. These values correlate with the so-called "transition region width", which is the distance required to change the dopant concentration by at least two orders-of-magnitude between the substrate doping level and the corresponding one on the "undoped" epi-layer. From the same experiment, 0.53, 0.68 and 0.09 /,m respectively have been reported. This means that the combination of RP and RT minimizes boron autodoping and solid state diffusion. Moreover this combination eliminates the need for backside sealing in p+ substrates and results in a very abrupt transition width for improved comple- mentary metal-oxide-semiconductor /CMOS) latch-up immunity [51.

Transition widths of 0. I /2m for antimony (10Is-1015 cm ~) and 0.15 #m for boron (1()~9-10~5 cm ~) have been reported in an "unconventional" reactor [2]. The low pressure range used is near the regime of molecular flow so that the escaping dopant atoms can leave the surface to diffuse away. This is more difficult to obtain in a "conventional" reactor in which the operation occurs in the laminar flow pressure regime (greater than 10 Tort) with large process gas volumes and large surface areas [3].

LT (less than 950°C) is adequate for thin submicrometer epitaxial structures for advanced CMOS, bipolar and BiCMOS. However, even

though LT epi-growth down to 850 °C in commercial radiantly heated barrel reactors at LP (less than 40 Torr) is now routinely achieved, LT may not always be the right choice. In fact, for an arsenic implanted substrate, to minimize autodoping, the prebake should take the form of an HT heat treatment which reduces the surface concentration and hence autodoping, by increasing the arsenic evaporation rate [35]. Thus for buried n + arsenic layers a HT/LP (greater than 1150 °C; less than 80 Torr) prebake followed by HT/LP (greater than 1050 °C; less than 40 Torr) is necessary to minimize autodoping. In the case of an antimony-doped substrate, autodoping is not an important problem, and phosphorus behaves like boron.

7. Loading effect

The loading effect is the growth rate (G) variation of the epitaxial layer according to the patterned and unpatterned surface ratio. Following lshitani et al. [36], when the silicon:silicon dioxide area ratio is small (between 10% and 40%) G is higher than in bare silicon. This "local loading effect" can then be interpreted as follows: between the masked and window areas there are species dependent spatial concentration varia- tions and as silicon is only deposited into the windows (selective deposition) it induces a variation in supersaturation corresponding to the concentration variation. Therefore, species flowing from SiO 2 could contribute to the epi-growth. One sug- gestion is to increase the HC1 injection to decrease this effect, the total system pressure being an important parameter.

We also observed a loading effect which con- cerns the total exposed silicon area in the wafer, in contrast to the local effect previously reported. Using the SiH4/H 2 system [37] the loading effect is observed for low Si: SiO 2 ratios at temperatures above 850 °C. The presence of large SiO 2 areas near the silicon windows, at relatively high temperatures, induces reactions such as H 2 + SiO 2 -~ SiO (g)+ H20 (g) which, by hydrogen consump- tion, enhances the silane decomposition and increases the growth rate [38].

In our pressure regime (below 10 Torr) DCS decomposition does not involve H 2 production and this loading effect is not observed at HT but it is at LT (below 850 °C). In fact, as also reported [22], when using DCS we are fully selective with no addition of HC1. Silicon nuclei forming on the

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silica mask are dissolved through the by-product HC1 according to Si* (mask) + 2HCI ~ SiC12 + H 2

(g). Thus, the produced SIC12 has enough mobility to migrate into the seed giving a higher G than in the case where there is no mask. No "local loading effect" was observed under this pressure regime.

According to Srinivasan and Meyerson [14] the difference in the relative G on different crys- tallographic planes becomes larger at reduced temperature. This enhanced growth anisotropy causes faceting. However, RP and lower G "off axis" serve to minimize this effect in addition to the pattern side-wall openings along the (100) direction instead of {110) [4].

8. Selectivity

Selective deposition of silicon onto patterned wafers has recently been the subject of several studies [5, 6, 22, 39]. A complement of SEG is ELO, i.e. the silicon growth within the seeds is subsequently laterally extended over the oxide. Growth is carried out until a continuous silicon film is formed over the S i O 2. Thus, the first phase of ELO is SEG.

Some problems appear in the SEG/ELO process [6].

(1) Oxide lifting or undercutting attributed to the prebake HT step. It decreases with decreasing temperature.

(2) Polycrystalline silicon on SiO2 can be incorporated into the ELO film. This effect is minimized by the addition of HC1 during growth.

(3) Defects are generated by the interaction between the oxide edge and ELO due to differ- ences in thermal expansion coefficients.

(4) Formation of a void in the SiO2 where the two overgrowing interfaces meet.

The best results obtained with a commercial reactor show about 100 defects cm 2 with an overgrowth ratio of one [6] showing that this technique is not yet mature and needs severe refine- ments.

To obtain selectivity in the pressure regime between 20 Tort and atmospheric pressure, the addition of HC1 is mandatory whatever the reacting gas is, silane or DCS. We have reported [24] two ways to obtain SEG between 1100 and 650 °C. The first includes D C S / H 2 without the addition of HCI; the second is the S i H 4 / H C 1 / H 2 system where the amount of HC1 represents just a few per cent of the Sill 4 concentration when the

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growth temperature is below 950°C. These results are characteristic of our system working in the 1 Tort pressure range.

More recently, Yew and Reif [40] have reported selectivity at 800°C using SiH4/H 2 in the mTorr range. The incubation time for silicon nucleation over the oxide is increased by the addition of H2 giving times as long as a few minutes which allow epi-growth in the seeds before nucleation on the oxide. The surface cleaning prior to deposition is made by UHV, UV and argon plasma. These results are confirmed by Murota et al. [41] where the incubation time is also several minutes if the oxide surface is suffi- ciently clean. To obtain full selectivity the adsorption site density has to be reduced by UHV or by the conversion of the adsorbed species into non- reactive species (e.g. HCI giving SiC12 ).

9. Conclusion

According to the present analysis it seems that today high quality low temperature silicon epitaxy is being achieved by means of: high/low temperature sequence; lower deposition pressures (below 100 Torr); constant G when using PECVD at low pressure; SEG which is also moving into production; "in situ" multilayers; epi-growth in submicrometer structures.

Some of the projects which are under development are photostimulated CVD, hot wall epitaxy at ultra low pressure, single wafer processing with RTP systems, SEG/ELO, etc.

For the ultralarge-scale integration (ULSI) levels required, the ability to control the dopant profile, which depends on the dopant incorporation mechanism, dopant species and substrate autodoping species, becomes very critical. How- ever, what might be the advantages of a process at low temperature? Some of them are: (a) better thickness uniformity because the deposition process changes from a flow-controlled mechanism at HT to a surface-controlled one at LT, thus making the thickness uniformity less dependent on the gas flow fluctuations; (b) lower reactor contaminants; (c) lower thermal stress and warpage; (d) abrupt doped layers; (e) SEG + ELO for three-dimensional structures; (f) new devices.

The epitaxial material obtained through these techniques is being used to test new devices such as the heterojunction bipolar transistor (HBT) using Si/Ge, for instance [42, 43].

One of the drawbacks is ~he cpitaxiai doping activation. At a high doping level (greater than 1017 cm-3) the problem of electrically activating the dopants will arise if / is close to 800°( ` hnpurity desorption and h~w (, are pointed ou! as potential problems.

So far epitaxial wafers have been used for bipolar devices and not for metal-oxide-semiconductors. This tendency can however be reversed owing to the development of new BiCMOS IC for ULSI. If this is the case, this will act as a booster to the development of these new epitaxial techniques which are at the moment still in the research and development stage.

However, epitaxy will stay for a while an "'art". and the right technique for a complex ULSt IC will depend strongly on the whole process anti this will be always in progress.

Acknowledgment

The authors would like to thank Mrs M. Timmins for reading the manuscript.

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43 See ,S)'mposium "A '; this Conference.

Documents

Epitaxial silicon chemical vapor deposition below atmospheric pressure