Fourteen-band hysteresis controller of the fifteen-level packed U cells converter

Youssef OUNEJJAR (IEEE member), Kamal AL-HADDAD (IEEE Fellow Member)

ÉCOLE DE TECHNOLOGIE SUPÉRIEURE

Canada Research chair in Electric Energy Conversion and Power Electronics Département de génie électrique,

1100, rue Notre-Dame Ouest, Montréal (Québec) H3C 1K3 E-mail : ounejjar@ieee.org

E-mail : Kamal.Al-Haddad@etsmtl.ca Abstract- In this paper, authors propose a novel fourteen-band hysteresis technique to control the fifteen level packed U cells (PUC) converter. This topology was first introduced in [1]. It combines advantages of the flying capacitor and the cascaded H-bridge topologies. The study of the novel converter allows the establishment of the switches gates signals equations. In case of rectifier operation, the proposed fourteen-band controller is designed to draw a sinusoidal line current with a unity power factor. Harmonics contents of line current and rectifier input voltage are then very reduced which permits the reduction of the rating of active and passive filters resulting on a very high energetic efficiency and a reduced installation cost. The fifteen level PUC transformerless inverter has the advantage to operate with a single DC source. A fourteen-band technique is performed to control the auxiliary DC buses and to draw a nearly sinusoidal load current. The proposed concepts were verified by simulations performed in the Matlab Simulink and SimPowerSystem environments. Index terms: packed U cells, multilevel converters, unity power factor operation, hysteresis controller

I. INTRODUCTION

Traditional multilevel converters like neutral point converters NPC proposed by Nabae, Takahashi and Akagi [2] and flying capacitors converters FCC proposed by Meynard and Foch [3] present many drawbacks if the number of voltage levels grows. In fact, the number of switches, diodes and capacitors grows excessively resulting on an expensive cost and their implementation becomes very complicated. When number of desired voltage level exceeds three, cascaded H-bridge inverters topology [4] becomes the optimal solution. This is due to their small

number of switches and passive components. However, this topology requires independent and isolated DC voltage sources, which leads to the use of transformers. In the last few years, many optimizations have been presented to improve the efficiency of these multilevel converters [5-11]. In these papers, authors propose multilevel inverters synthesizing a large number of levels with improved output waveforms characterized by a low distortion and smaller filter size. The packed U cells converter combines advantages of flying capacitors converter and cascaded H-bridges one. It uses small number of switches, diodes and capacitors [12]-[14]. In [15], authors propose a fifteen level inverter topology that uses seven DC sources and twenty eight semi-conductor devices. Whereas, in [16], authors propose a thirty one level inverter using only four DC sources and sixteen semi-conductor devices. The two propositions are based on classic cascaded H-bridges topology. Flying capacitors and diode clamped topologies are limited to three levels, because of the required excessive number of passive and active components when the number of voltage level exceeds three.

Table 1: Comparison between the proposed 15-level converter and usual 15-level ones

Diode clamped

Flying capacitors

Cascaded H-bridges

Proposed converter

Capacitor 14 14 7 3 Clamped

diodes 26 0 0 0

Switches 28 28 28 8

Table 1 shows a comparison toward concurrent multilevel converters in terms of number of capacitors, number power devices, and in terms of number of diodes. Both pulse width modulation and hysteresis current techniques are used to control multilevel converters. The

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second strategy has very simple implementation but it presents a sporadic switching frequency, whereas the first strategy has a complex implementation but is characterized by a constant switching frequency. The hysteresis control technique has proven to be the most suitable solution for all the applications of current controlled voltage source inverters where performance requirements are more demanding, such as active filters, drives and high-performance ac power conditioners, albeit at the expense of variable switching frequency. However, some approaches are available in the literature to obtain fixed switching frequency under hysteresis control [17]. In this paper, a novel fourteen-band hysteresis technique is proposed to control the PUC fifteen level converter in both rectifier and inverter operation. The proposed technique allows a nearly sinusoidal line or load current with a fifteen level voltage input (output) voltage in case of rectifier (inverter) operation.

II. PRESENTATION OF THE PACKED U CELLS TOPOLOGY

A topological optimization of the classic cascaded H-bridge inverters results on a new competitive topology which use small number of passive and active components and avoid the use of transformers (figure1.a). A comparison of the PUC topology toward other fifteen level converters is given in table1. The fifteen levels neutral point converter NPC and the flying capacitors converter FCC use a very high number of switches, diodes, and capacitors. The PUC topology, however, uses only eight switches (see figure 1.b).

(a)

(b) Fig.1. Fifteen level packed U cells (PUC)

a- transformerless inverter b- rectifier

III. FOURTEEN BAND HYSTERESIS CONTROLLER OF THE TRANSFORMERLESS FIFTEEN LEVEL PUC INVERTER

In figure 1.a, the AC load voltage reference can be generated by the following equation:

dtikikV LiLpan ∫+= ~~11 (1)

Where: LLL iii −= *~, *

Li is the load current reference The capacitor voltage is controlled using a PI regulator such that:

( ) ( )dtvkvkdtvkvki ipipL ∫∫ +++= 33332222* ~~~~

(2)

Where: 1*12

~cc vvv −= , 2

*23

~cc vvv −= , *

1cv and *2cv are the

capacitors voltages references In order to generate fifteen levels output voltage, one must

control the capacitors voltages set point equal to 7E and

73E . Thus, the fifteen level voltages are therefore obtained

as given in table 2. iT and iT′ switches operate complementarily, thus, only Ti switches are used. When actual load current is lower that its reference, then, the application of a positive voltage across the load allows their rapprochement Thus, the positive voltages (sector I in figure 2) are applied when the current error Δi, which is the difference between actual load current and its reference, is negative. Contrariwise, the negative voltages (sector II) are applied when the current error is positive. The fifteen states and their transition conditions are depicted in figure 3.

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Fig.2. Fourteen band hysteresis controller of the 15-level PUC inverter

Table 2: Switching table of the proposed fifteen level inverter

Voltage level

DC voltage combination

Switches pulses

T1 T2 T3 T4

1 E 1 0 0 0 2 E-Vc1+Vc2 1 0 1 0 3 E-Vc2 1 0 0 1 4 E-Vc1 1 0 1 1 5 Vc1 1 1 0 0 6 Vc1-Vc2 1 1 0 1 7 Vc2 1 1 1 0 8 0 1 1 1 1 9 -Vc2 0 0 0 1

10 Vc2-Vc1 0 0 1 0 11 -Vc1 0 0 1 1 12 Vc1-E 0 1 0 0 13 Vc2-E 0 1 1 0 14 Vc1-Vc2-E 0 1 0 1 15 -E 0 1 1 1

IV. SIMULATION RESULTS

Simulation was performed in Matlab Simulink and SimPowerSystems environment. The system parameters are the following: Auxiliary DC bus capacitor 4 000 µF Load inductance 15 mH Load resistor 30 Ω Principal DC link voltage E 140V The auxiliary DC buses (Vc1 and Vc2 in figure 1.a) are respectively controlled to the three-seventh and the seventh of the principal one E, which is maintained at 140V.

Figure 4 shows a good regulation of the two auxiliary DC buses voltages Vc1 and Vc2 which remain, in steady state, around their references 60V and 20V respectively. Load current is perfectly sinusoidal as shown in figure 5. The load voltage, which is the inverter output voltage, is nearly sinusoidal (see figure 6) with a THD around 6.59% as shown in figure 7.

Fig.3. Chart flow of the fourteen band hysteresis controller

477

0 1 2 3 4 5 6 7 8 9 10-20

0

20

40

60

80

100

120

140

160

Simulation time (s)

DC b

uses

vol

tage

s (V

)

Fig.4. Evolution of the auxiliary DC bus voltage

3 3.01 3.02 3.03 3.04 3.05 3.06-5

-4

-3

-2

-1

0

1

2

3

4

5

Simulation time (s)

Load

urren

t (A)

Fig.5. Load current

3 3.005 3.01 3.015 3.02 3.025 3.03 3.035 3.04 3.045 3.05-160

-140

-120

-100

-80

-60

-40

-20

0

20

40

60

80

100

120

140

160

Simulation time (s)

Inve

rter o

utpu

t vol

tage

(V)

Fig.6. Inverter output voltage

(a)

(b)

Fig. 7. (a) Harmonics contents of load voltage (b) loop effect on (a)

V. NOVEL FOURTEEN BAND HYSTERESIS CONTROLLER OF THE FIFTEEN LEVEL PUC RECTIFIER

Applying the Kirchhoff voltage law to the input of the 15-level PUC rectifier shown in figure 1.b leads to the following equation:

s

anes

Lvv

dtdi −

= (3)

In each state of the 15-level PUC rectifier, the voltage van is constant as shown in table 2. Thus, when the source voltage

and van are positives then dtdis is positive and the line

current increases. Contrariwise, it decreases. When van is positive the capacitors will be in charge or discharge mode if the source voltage is positive or negative respectively. The capacitors are not in charge or discharge mode when van is null. In this case, the line current will increase or decrease if the source voltage is positive or negative respectively. Assuming a unity power factor operation, one can observe that switch T1 is ON only when the current error Δi is negative and the source voltage ve is positive. Thus, the T1 switch pulse can be given by:

( ))sgn(1).sgn(1 ivT e Δ−= (4) Where:

ss iii −=Δ * , is is the line current and is* is its reference

⎩⎨⎧

<≥

=0001

)sgn(x if x if

x i vx e Δ= ,

The analysis of the ON/OFF states of T2, T3 and T4 switches leads to the subdivision of current error into six regions designated by Hi, 6,5,4,3,2,1∈i . These regions can be defined by the following equations:

478

⎩⎨⎧ ≤Δ<

=else 0

0i4.h- if 11H (5)

⎩⎨⎧ ≥Δ

=lse 0

.h3i if 12 e

H (6)

⎩⎨⎧ ≤Δ<−≤Δ<

=else 0

0i2.h-or .4i6h- if 13

hH (7)

⎩⎨⎧ Δ<≤Δ<

=else 0

i5.hor .3ih if 14

hH (8)

⎪⎩

⎪⎨

⎧≥Δ≤Δ<

≤Δ<≤Δ<=

else 06.h ior .5i4.hor .3i2.hor i0 if 1

5 hhh

H (9)

⎪⎩

⎪⎨

⎧≤Δ<−≤Δ<−≤Δ<−≤Δ<

=else 0

0ih-or .2i3.h-or .4i5.h-or .6i7.h- if 1

6 hhh

H (10)

Where h is the hysteresis bandwidth. The gates pulses of switches T1, T2 and T3 are given by:

⎪⎩

⎪⎨

⎧

−+=−+=−+=

654

433

212

)).sgn(1().sgn()).sgn(1().sgn()).sgn(1().sgn(

HvHvTHvHvTHvHvT

ee

ee

ee

(11)

The amplitude of line current reference is given by:

( ) ( )

( ) ⎟⎠⎞

⎜⎝⎛ +−+

⎟⎠⎞

⎜⎝⎛ +−+⎟

⎠⎞

⎜⎝⎛ +−=

sKKVV

sKKVV

sKKVVA

ipcrefc

ipcrefc

ipcrefc

3333

2222

1111

(12)

The line current reference is then generated by multiplying A and the unity vector to ensure a unity power factor operation as shown in figure 8.

Fig.8. Proposed fourteen band hysteresis control technique of the 15-level packed U cells rectifier

VI. SIMULATION RESULTS

The system parameters are the following: Principal and auxiliary DC buses capacitors 4 000 µF Line inductance 3 mH Load resistor 100 Ω Supply network voltage (ve) 120V rms The reference of the principal DC link bus is 270V. Thus the reference Vc1 and Vc2 are 38.57V and 115.29V respectively. Figure 9 shows that the voltages of the principal and auxiliary DC buses are well controlled around their references. The rectifier input voltage is constituted from fifteen level voltages (270, 231.43, 192.86, 154.29, 115.71, 77.14, 38.57, 0, -38.57, -77.14, -115.71, -154.29, -192.86, -231.43, -270) as shown in figure 10. The total harmonics distortion THD of the rectifier input voltage is 29.56% as shown in figure11. The unity power factor operation is well performed as shown in figure 12. Line current is perfectly sinusoidal and its total harmonics distortion THD is about 2.78% which can be lower with a smaller hysteresis band (see figure 13). The switching frequency is sporadic, which is the main characteristic of any hysteresis controller. However, it can be limited at low frequencies by acting on the hysteresis band.

0 2 4 6 8 10 12 14 16-38.57

0.00

38.57

77.14

115.71

154.28

192.86

231.43

270

308.57

Simulation time (s)

DC

link

and

aux

iliar

y ou

tput

vol

tage

s (V

)

Fig.9. Rectifier output voltages

14.23 14.235 14.24 14.245 14.25 14.255 14.26 14.265 14.27 14.275-308.57

-270

-231.43

-192.86

-154.29

-115.72

-77.15

-38.58

-0.01

38.56

77.13

115.7

154.27

192.84

231.41

270

308.57

Simulation time (s)

Rec

tifie

r inp

ut v

olta

ge (V

)

Fig.10. Rectifier input voltage

479

Fig. 11. Harmonics contents of rectifier input voltage

14 14.005 14.01 14.015 14.02 14.025 14.03-200

-150

-100

-50

0

50

100

150

200

Simulation time (s)

Net

wor

k su

pply

vol

tage

and

line

cur

rent (

V, A

)

Fig.12. Source voltage and line current

Fig. 13. Loop effect of the harmonics contents of line

current

VII. CONCLUSION

A novel fourteen band hysteresis control technique of the fifteen level packed U cells converter is presented in this paper. The proposed controller allows a nearly sinusoidal current both in rectifier or inverter operation. The DC link buses voltages are well controlled and track their references.

The rectifier input voltage or the inverter output voltage has fifteen level voltages which permits the reduction of the active and passive filters rating resulting on a very high energetic efficiency and a reduced installation cost. The good dynamics of the system prove the efficiency of the proposed controller.

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