6
Large Low-CTE Glass Package-to-PCB Interconnections with Solder Strain-Relief Using Polymer Collars Gary Menezes, Vanessa Smet, Makoto Kobayashi + , Venky Sundaram, Pulugurtha Markondeya Raj, and Rao Tummala 3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, USA + Namics Corporation, Niigata, Japan Abstract This paper reports the use of circumferential polymer collars as a strain-relief mechanism to improve the fatigue life of low-CTE package-to-PCB solder interconnections, while preserving SMT-compatibility and reworkability. Acting as a partial underfill, the polymer- collar serves to block shear deformation at the solder-package interface, and redistributes the load to reduce the overall plastic strain concentration in the solders. It also suppresses failure initiation from defective surface sites and,thus further enhances reliability. Ultra-thin glass 100μm interposers were fabricated in 18.4 mm x 18.4 mm size to model, design and demonstrate the reliability enhancement with the polymer-collar approach. The detailed interposer design and fabrication process with laminated dielectric and metallization layers on both sides is presented. A new class of epoxies with low modulus, without the incorporation of silica fillers, was used to act as the polymer collars. The polymer collars are formed by spin- coating with an optimized thickness to provide the best compromise between the effective strain relief and reworkability. Board-level assembly was performed using standard SMT processes for glass interposers with and without polymer collars. Thermal cycling reliability testing (-40°C to 125°C) of interposers, assembled on PCBs with and without polymer collars for various thicknesses of the collar was performed. Introduction Large, low-CTE packages are emerging as major need to interconnect multiple chips with fine-pitch chip-level interconnections with advanced RDL ground rules, both for high-performance 2.5D packages and ultrathin consumer products. These low-CTE packages are also needed to minimize stress on the ultra-low k on-chip dielectrics. This low-CTE package approach, however, creates CTE-mismatch related stress issues for package-to-board-level interconnections, resulting in degradation of board-level reliability. Innovative, low-cost, interconnection technologies at finer pitches are therefore highly sought after for direct assembly to the board, thus eliminating the need for additional interposer packaging level. For wider acceptance of low-CTE packages in high-volume production, it is also critical to assemble them using standard SMT with high degree of automation, reduced labor costs and higher production rates. A number of unique stress-relief interconnection approaches have been reported in the literature, originally developed for WLP, but then extending them to solve the board-level interconnection reliability challenges. The G-helix [1] and stretched-solder interconnections [2] are based on compliant metal interconnection structures to provide stress- relief and improve the reliability. The double solder ball wafer-level technique by IZM [3] is another such approach to improve the interconnection compliance. Ball-on-polymer [4] and ELAStec WLP [5] place the joints on a layer of compliant polymer to reduce the strain in the joint itself. Wide Area Vertical Expansion (WAVE) [6] technology introduces a compliant low-modulus layer between the die and the interconnection layer. These approaches compromise the electrical performance, increase process complexity, or create additional challenges by increasing the package height, or use non-standard assembly processes. GT-PRC is pioneering novel low-cost stress-relief approaches with minimal additional process steps using standard package- to board SMT processes by extending them to large package sizes at fine pitch. Past work on such glass package-to-PCB interconnections at GT-PRC used a dielectric strain buffer on either side of the glass to enhance reliability of 7.2 mm x 7.2 mm packages. Two variations of glass CTE were studied, 3.8 ppm/K and 9.8 ppm/K. Both variations of glass were shown to give better reliability than silicon interposer at board level, undergoing up to 1500 thermal cycles before the first occurrence of joint failure [8]. This paper reports the use of circumferential polymer collar as a strain-relief mechanism to improve the fatigue life of low CTE package-to-PCB solder interconnections, while preserving SMT-compatibility and reworkability. Acting as a partial underfill, the polymer collar serves to block shear deformation at the solder-package interface, and redistributes the load to reduce the overall plastic strain concentration in the solders. It starts with thermo-mechanical modeling to predict the solder joint strains ,leading to design of the polymer-collar structure for meeting the reliability requirements, followed by process development to achieve the polymer-collar structure design, large glass package test- vehicle fabrication and surface mount assembly process for high-volume manufacturing, and finally ends with reliability characterization and model-to-hardware correlation. Finite Element Modeling Two-dimensional half-symmetry models of glass interposers were built along the diagonal of the package to simulate the plastic strain in the furthest solder joint. The left boundary of the package was given symmetry boundary conditions with the bottom corner pinned. The modeled assembly was first subjected to a drop in temperature from 260˚C to 25˚C to simulate the cool-down phase of the SMT reflow process. Five thermal cycles between -40˚C and 125˚C (following the JESD22-A106B thermal 978-1-4799-2407-3/14/$31.00 ©2014 IEEE 1959 2014 Electronic Components & Technology Conference

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Page 1: Large Low-CTE Glass Package-to-PCB Interconnections with ... · GT-PRC is pioneering novel low-cost stress-relief approaches with minimal additional process steps using standard package-

Large Low-CTE Glass Package-to-PCB Interconnections with Solder Strain-Relief Using Polymer Collars

Gary Menezes, Vanessa Smet, Makoto Kobayashi

+, Venky Sundaram, Pulugurtha Markondeya Raj, and Rao Tummala

3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, USA

+ Namics Corporation, Niigata, Japan

Abstract This paper reports the use of circumferential polymer

collars as a strain-relief mechanism to improve the fatigue life

of low-CTE package-to-PCB solder interconnections, while

preserving SMT-compatibility and reworkability. Acting as a

partial underfill, the polymer- collar serves to block shear

deformation at the solder-package interface, and redistributes

the load to reduce the overall plastic strain concentration in

the solders. It also suppresses failure initiation from defective

surface sites and,thus further enhances reliability.

Ultra-thin glass 100µm interposers were fabricated in

18.4 mm x 18.4 mm size to model, design and demonstrate

the reliability enhancement with the polymer-collar approach.

The detailed interposer design and fabrication process with

laminated dielectric and metallization layers on both sides is

presented. A new class of epoxies with low modulus, without

the incorporation of silica fillers, was used to act as the

polymer collars. The polymer collars are formed by spin-

coating with an optimized thickness to provide the best

compromise between the effective strain relief and

reworkability. Board-level assembly was performed using

standard SMT processes for glass interposers with and without

polymer collars. Thermal cycling reliability testing (-40°C to

125°C) of interposers, assembled on PCBs with and without

polymer collars for various thicknesses of the collar was

performed.

Introduction Large, low-CTE packages are emerging as major

need to interconnect multiple chips with fine-pitch chip-level

interconnections with advanced RDL ground rules, both for

high-performance 2.5D packages and ultrathin consumer

products. These low-CTE packages are also needed to

minimize stress on the ultra-low k on-chip dielectrics. This

low-CTE package approach, however, creates CTE-mismatch

related stress issues for package-to-board-level

interconnections, resulting in degradation of board-level

reliability. Innovative, low-cost, interconnection technologies

at finer pitches are therefore highly sought after for direct

assembly to the board, thus eliminating the need for additional

interposer packaging level. For wider acceptance of low-CTE

packages in high-volume production, it is also critical to

assemble them using standard SMT with high degree of

automation, reduced labor costs and higher production rates.

A number of unique stress-relief interconnection

approaches have been reported in the literature, originally

developed for WLP, but then extending them to solve the

board-level interconnection reliability challenges. The G-helix

[1] and stretched-solder interconnections [2] are based on

compliant metal interconnection structures to provide stress-

relief and improve the reliability. The double solder ball

wafer-level technique by IZM [3] is another such approach to

improve the interconnection compliance. Ball-on-polymer [4]

and ELAStec WLP [5] place the joints on a layer of compliant

polymer to reduce the strain in the joint itself. Wide Area

Vertical Expansion (WAVE) [6] technology introduces a

compliant low-modulus layer between the die and the

interconnection layer. These approaches compromise the

electrical performance, increase process complexity, or create

additional challenges by increasing the package height, or use

non-standard assembly processes.

GT-PRC is pioneering novel low-cost stress-relief

approaches with minimal additional process steps using

standard package- to board SMT processes by extending them

to large package sizes at fine pitch. Past work on such glass

package-to-PCB interconnections at GT-PRC used a dielectric

strain buffer on either side of the glass to enhance reliability of

7.2 mm x 7.2 mm packages. Two variations of glass CTE

were studied, 3.8 ppm/K and 9.8 ppm/K. Both variations of

glass were shown to give better reliability than silicon

interposer at board level, undergoing up to 1500 thermal

cycles before the first occurrence of joint failure [8].

This paper reports the use of circumferential polymer

collar as a strain-relief mechanism to improve the fatigue life

of low CTE package-to-PCB solder interconnections, while

preserving SMT-compatibility and reworkability. Acting as a

partial underfill, the polymer collar serves to block shear

deformation at the solder-package interface, and redistributes

the load to reduce the overall plastic strain concentration in

the solders. It starts with thermo-mechanical modeling to

predict the solder joint strains ,leading to design of the

polymer-collar structure for meeting the reliability

requirements, followed by process development to achieve the

polymer-collar structure design, large glass package test-

vehicle fabrication and surface mount assembly process for

high-volume manufacturing, and finally ends with reliability

characterization and model-to-hardware correlation.

Finite Element Modeling Two-dimensional half-symmetry models of glass

interposers were built along the diagonal of the package to

simulate the plastic strain in the furthest solder joint. The left

boundary of the package was given symmetry boundary

conditions with the bottom corner pinned.

The modeled assembly was first subjected to a drop in

temperature from 260˚C to 25˚C to simulate the cool-down

phase of the SMT reflow process. Five thermal cycles between

-40˚C and 125˚C (following the JESD22-A106B thermal

978-1-4799-2407-3/14/$31.00 ©2014 IEEE 1959 2014 Electronic Components & Technology Conference

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shock standard) were applied. The ramp-up and ramp-down

times were 1 minute and the dwell time at the temperature

extremes was 5 minutes. Equivalent plastic strain range was

extracted after cycling.

Lead-free SAC105 solder material was used during

modeling and test-vehicle fabrication due to better

performance under drop test [9]. Solder was modeled as a

visco-plastic material using parameters derived from Anand’s model. Copper was modeled as a bilinear elastic-plastic

material while all other materials were considered elastic

(Table 1). The viscosity of polymer materials is neglected for

the temperature range in consideration.

Table 1: Material properties used for FEA

Material

E (GPa)

CTE (ppm/˚C)

Poisson’s ratio

Material model

Glass (High CTE)

74 9.8 0.23 Elastic

Glass (Low CTE)

77 3.8 0.22 Elastic

Silicon 130 2.7 0.28 Elastic

FR-4 24 16 0.3 Elastic Solder Temp.

dep. 22 0.34 Visco-plastic

Copper 121 17.3 0.3 Elastic-plastic

Finite element modeling results and analysis FEA was used to analyze the strain relief mechanism

behind the polymer collar approach. Five variations in

polymer height on the solder ball were simulated so as to

provide guidelines for experimental design (Figure 1, Table

2).

Figure 1: Variations in polymer collar height

Table 2: Variations in polymer collar height

Collar type

Height between solder balls

UF Collar material as underfill

T0 ~170 µm

T1 ~110 µm

T2 ~80 µm

T3 ~55 µm

Strain relief mechanism

A high-CTE glass package assembly at 18.4 mm x 18.4

mm size was simulated with each of the collar types. Plastic

strain was extracted at the four critical locations on the outer

most solder ball (Figure 2).

Figure 2: Critical locations for maximum solder plastic

strain with (left) and without (right) polymer collar

The underfilled structure shows the same plastic strain at

all four points on the joint (Figure 3). With the addition of the

polymer collar, the region of high plastic strain was

transferred from the package interface to that between the

joint and collar, decreasing the package side strain as

compared to the UF case. Presence of the collar reduces

plastic strain range at all four critical points, though maximum

strain range is still seen on the board side. The collar cannot

be applied on the board side as this would hinder

reworkability.

A trend of decreasing strain range with increasing collar

thickness is seen from the results of these simulations. The

thickest collar variation (T0) provides the largest buffer to

shear deformation resulting in the lowest strain range at the

bottom left of the joint. Reduction in strain range for this case

is 16.7%. The polymer collar therefore acts as a partial under-

fill.

Figure 3: Plastic strain range at the 4 critical locations on the

joint

Glass panel fabrication Glass-interposer test vehicles were designed at a

body size of 18.4 mm x 18.4 mm. High CTE, 100 µm thick

interposers were fabricated with two dielectric build-up layers

RXP-4M (20 µm) and ZS-100 (22.5 µm), laminated on either

side of the 6” x 6” bare CF-XX glass panels provided by

Asahi Glass Company. The dielectric materials were procured

from Rogers Corporation and Zeon Corporation respectively.

The panels were then metalized to provide patterning for test

daisy-chain structures. Two variations in package pads were

introduced with non-solder mask defined (NSMD) pads

created with dry-film photosensitive solder resist. The second

variation with resin mask defined (RMD) pads were created

by laminating an additional layer of ZS-100 over the

patterning and drilling holes in the polymer to create openings.

1960

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ENEPIG was used as the surface finish on the copper

pads (carried out at Atotech, Germany). The interposer

fabrication flow is depicted in Figure 4. The panels were then

sent to Nanium for attachment of 250 µm solder BGAs by ball

drop and interposer dicing.

Figure 4: Panel-level fabrication process flow for glass interposers. (a)-(g): Substrate cleaning, dielectric lamination, seed copper, lithography, electroplating, seed etching, surface finish and solder resist processing.

Polymer collar process Epoxy materials without fillers were spin-coated onto

the BGA side of the diced-glass interposers to form the

circumferential collars. The interposers were then oven dried

at 70 ˚C for 1 hour to allow the solvent content to evaporate

(Figure 5).

Figure 5: Polymer collar application and drying process

When a square substrate is coated with polymer

collar, its corners experience high air friction resulting in a

higher rate of evaporation at these locations. The material at

the corners dries up and impedes flow of material, being

driven radially outward by the centrifugal forces. This

behavior leads to material build-up at the corners of the

substrate.

Figure 6: Material build-up at substrate corners during

spin coating

The shape of the larger 18.4 mm interposers deviates

even more from an ideal circular substrate. Trials using a

simple ramp-up and dwell process resulted in highly non-

uniform deposition (Figure 7).

Figure 7: Non-uniform coating on 18.4mm interposer

Two enhancements were therefore used to improve

spin-coating uniformity. Firstly, dummy interposers were

placed around the test interposer to simulate a larger substrate

size and eliminate corner effects (Figure 8).

Figure 8: Enhancement to make region around test

substrate radially uniform

In addition, the coating profile was changed to

include spreading and uniformity phases to allow the material

to deposit uniformly over the surface of the test interposer

(Figure 9, 10). The final height of coated material depends on

the spin coating rate applied in the uniformity phase. It is

therefore possible to control the height of the polymer collar

using this parameter. The maximum variation in coated height

after these enhancements was about 20% (Figures 11,12).

Figure 9: Coating profile for 18.4 mm interposers

1961

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Figure 10: Uniform coating on 18.4 mm interposers

Figure 11: Measured thickness of deposited collar material

on 18.4 mm interposers

Figure 12: Cross sections of uniformly deposited 18.4 mm

interposers

Polymer collar residue removal

SEM imaging was used to confirm the presence of a

polymer residue on the ball surface after the application

process (Figure 13). Although the material is designed to flow

from the bonding area, this residue could be perceived as

contamination of the solder balls by automated defects

detection systems used in industry. Samples were assembled in

order to check for contamination, however, no difference in

the surface topography and chemical composition was seen at

the solder-pad interface after careful analysis of the

intermetallic compounds by SEM/EDX. The next generation

of collar material may contain fillers, making residue removal

a possible challenge.

Figure 13: Coating with polymer collar leaves a residue on

the ball surface

With the objective of manufacturability, three options for

residue removal were explored.

1. Plasma etching The parameters used in the plasma etching approach are listed

in Table 4. It was observed that while removing residue from

the surface of the ball, etching also attacks the circumferential

collar (Figure 14). In addition, longer etching times can

change the microstructure of the ball surface, which is not

acceptable by industry standards.

Table 3: Plasma etching conditions Parameter Condition

Composition CHF3 (10 sccm) / O2 (50 sccm) Pressure 10 mtorr Power 300 W Time 15 and 30 minutes

Figure 14: Side profile of solder ball before (left) and after

(right) 15 minutes of plasma etching 2. Sandblasting

Sand blasting of the ball surface was explored as a possible

approach (Table 5). With 250 µm diameter pumicite, the

solder surface and, in some samples, the interposer suffered

serious damage. Trials done with 35 µm diameter pumicite

suffered no visible damage up to 10 seconds of processing.

Pumicite was found embedded in the collar material for all

variations in process time.

Table 4: Sand blasting conditions Medium / grain size: pumicite / 250 µm

Pressure 30 psi Time (sec) 10, 20, 30

Medium / grain size: pumicite / 35-75µm Pressure 25 psi

Time (sec) 5, 10, 30

While this process removes the residue from the ball surface,

it is very hard to optimize. Damage to the ball and embedded

particles that compromise the integrity of the collar prevent it

from being used as a manufacturable solution.

Solvent cleaning Acetone was used to wipe the ball surface right after the

polymer drying stage. As the residue is not cured at this stage,

it is easily removed (Figure 15). The material forming the

collar remains intact as the solvent comes in contact with only

the top surface of the ball (Figure 16).

Figure 15: Close-up of ball surface before (left) and after

(right) solvent wipe cleaning

1962

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Figure 16: The polymer collar remains intact after

cleaning

A comparison of the results from the three

approaches shows that the solvent wipe method is most

effective in removing the polymer-collar residue with

negligible damage to the collar. The process can possibly be

implemented by dipping the balls in acetone and then IPA

using infrastructure similar to that used for flux dipping prior

to assembly.

Assembly for reliability

Tacky flux was first applied to the PCB, followed by a

pick-and-place step using a Finetech Matrix flip-chip bonder

with a 20 mm x 20 mm pre-leveled vacuum-locked spring

gimbal tool. Reflow conditions were optimized to match the

recommended profile by the flux supplier. Less than 25%

voiding was achieved on assembled samples as required by

industry standards.

Assembly process evaluation

In samples assembled with collar, leakage of polymer

material onto the PCB was observed. This occurs because the

melting point of the collar material is lower than the reflow

temperature. The most severe occurrence of board-side

leakage is seen in the case of thick collar. A compromise has

therefore to be made between buffering capability of the

thicker collar and board-side leakage which hinders

reworkability.

Figure 17: Leakage of material onto ball and PCB after

assembly with 90µm thick collar

Self-alignment of solder joints

An important consideration for assembly with

circumferential collars is the ability of the solder joints to self-

align during reflow. Samples with thickest collar, serving as

the worst possible scenario, were used to evaluate self-

alignment capability. Increasing degrees of misalignment were

introduced during the pick-and-place process. Samples were

x-ray imaged before and after reflow to document the

introduced misalignment and evaluate alignment after reflow.

The experiment showed that introducing a thick

collar around the solder balls does not prevent self-alignment

even with the interposer is off by 3/4 of the PCB pad ( ~170

µm) unless the ball is placed in contact with multiple pads.

This verifies that the polymer collar is compatible with the

SMT process.

Preliminary Reliability assessment Reliability testing was performed using JESD22-A104D

standards for thermal cycling with assembly, following a pre-

conditioning step comprising of 2 additional reflows at 260

°C. Thermal cycling was then performed between -40 °C and

125 °C with a 15 minute dwell time and a rate of 1 cycle/hour.

A dummy Si die (12mm x 12mm and 100µm thickness) was

underfilled on the interposer to see the impact of die-attach on

board-level reliability. The daisy-chain resistances were

measured after every 50 cycles. No failures were detected

during the testing. The reliability characterization data

indicates that polymer collar was successful in preventing

solder-joint reliability failures.

Conclusion

Solder-pad interfaces on the package side play a critical

role in determining the board-level interconnection reliability,

particularly with low CTE packages. This paper develops and

demonstrates a polymer-collar approach to alleviate the

failures at such interfaces. The polymer collar, which forms a

circumferential layer around the solder joint on the package

side, blocks the shear deformation of the joint at this interface,

transferring the high plastic strain to the lower side of the ball

which has lower propensity for failure. The collar therefore

acts as a partial under-fill and maintains the reworkability of

the assembly. This circumferential polymer collar is deposited

around the solder ball on the package side by spin-coating.

SMT-compatible assembly processes for large 18.4 mm x 18.4

mm glass interposers with polymer collars were demonstrated.

Results demonstrate that the reliability of low-CTE glass

interposers on organic packages or baords is significantly

enhanced with this polymer collar approach.

1963

Page 6: Large Low-CTE Glass Package-to-PCB Interconnections with ... · GT-PRC is pioneering novel low-cost stress-relief approaches with minimal additional process steps using standard package-

Acknowledgments This study was supported by the “Interconnection and

Assembly” focused program at the Georgia Tech Packaging

Research Center. The authors would like to thank industry

mentors, especially Dr. Jaesik Lee from Qualcomm, for their

active guidance, suggestions and support. The authors would

also like to thank Asahi Glass Company for providing glass

substrates, Namics Corporation for their polymer collar

material, Atotech for surface finish processing, Nanium for

BGA attachment and interposer singulation, and Zeon

Corporation and Rogers Corporation for providing dielectric

materials. The authors also thank the Toshitake Seki from

NTK/NGK, Yoichiro Sato from Asahi Glass Company and

Akira Mieno from Atotech for their support and advice on

fabrication, and Anna Stumpf and Anne Matting for their

experimental contribution.

References 1. Zhu, K., Ma, L., Sitaraman, S., “Development of G-Helix

Structure as Off-Chip Interconnect,” Journal of Electronic Packaging, June 2004.

2. Lim, S.S., Rajoo, R., Wong, E.H., Hnin, W.Y., “Reliability Perfornance of Stretch Solder Interconnections,”

International Electronic Manufacturing Technolgy, 2006.

3. Topper, M., et. al., “Wafer Level Package using Double Balls,” International Symposium on Advanced Packaging Materials, 2000.

4. Varia, B., Fan, X., Han, Q., “Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large

Array Wafer Level Packages,” ICEPT-HDP, 2009.

5. Dudek, R., et. al., “Thermo-mechanical Design of Resilient

Contact Systems for Wafer Level Packaging,” 7th

International Conference on Thermal, Mechanical and

Multiphysics Simulation and Experiments in Micro-

Electronics and Micro-Systems, 2006.

6. Li, D., et. al., “A Wide Area Vertical Expansion (WAVE) Package Process Development,” IEEE Electronic Components and Technology Conference, 2001..

7. Bakir, M., et. al., “Sea of Leads Compliant I/O interconnect Process Integration for the Ultimate Enabling

of Chips with Low-k Interlayer Dielectrics,” IEEE Transacations on Advanced Packaging, 2005.

8. Qin, X., Kumbhat, N., Sundaram, V., Tummala, R.,

“Highly-Reliable Silicon and Glass Interposers-to-Printed

Wiring Boaring SMT Interconnections: Modeling, Design,

Fabrication and Reliability,” 62nd IEEE Electronic

Components and Technology Conference, 2012.

9. Pandher, R., et.al., “Drop Shock Reliability of Lead Free

Alloys – Effect of Micro-Additives,” ECTC, 2007.

1964