lec06-pipelining-mips.ppt

8/9/2019 lec06-pipelining-mips.ppt

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Lecture 6: PipeliningMIPS R4000 and More

Kai [email protected]

http://list.zju.edu.cn/kaibu/comparch


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Lab 2Demo due April 15

Report due April 1

Assignment 2

http://list !"u edu cn/#aibu/comparch/Assignment$2 pd%

http://list.zju.edu.cn/kaibu/comparch/Assignment-2.pdfhttp://list.zju.edu.cn/kaibu/comparch/Assignment-2.pdfhttp://list.zju.edu.cn/kaibu/comparch/Assignment-2.pdfhttp://list.zju.edu.cn/kaibu/comparch/Assignment-2.pdf


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Appendi& ' ($' )


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Multic cle ,P *peration

! ,loating$point 3,P operations takemore time than inte"er operations do

! #o complete an $% op in 1 cc:a slo& clock'man( lo"ic in $% units'


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Multic cle ,P *peration

! ,P pipelineallo& )or a lon"er latenc( )or op*

t&o chan"es o+er inte"er pipeline:repeat ,-*use multiple $% )unctional units*


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,P Pipeline


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*utline

! ultic(cle $% perations! 0azards and $or&ardin"

! %2 R3444 %ipeline


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*utline


! %2 R3444 %ipeline


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,P Pipelineloads and stores

integer ALU operationsbranches

FP addFP subtract

FP conversion

FP and integer multiplier

FP and integer divider


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,P Pipeline

! ,- is not pipelined! o other instruction usin" that

)unctional unit ma( issue until thepre+ious instruction lea+es ,-

! ) an instruction cannot proceed to ,-6the entire pipeline behind thatinstruction &ill be stalled


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,P Pipeline

! Latencthe number o) inter+enin" c(clesbet&een an instruction that produces aresult and an instruction that uses theresult

! Initiation/Repeat Inter5althe number o) c(cles that must elapsebet&een issuin" t&o operations o) a

"i+en t(pe


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,P Pipeline

Essentially, pipeline latency is 1 cycleless than the depth of the execution

pipelinee.g., FP add takes 4 stages


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enerali!ed ,P Pipeline

! ,- is pipelined 7e8cept )or $% di+ider9! Additional pipeline re"isters

e.".6 D/A1

FP divider: 24 CCs


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enerali!ed ,P Pipeline

! ,8ampleitalics: sta"e &here data is needed

bold : sta"e &here a result is a+ailable


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*utline


! %2 R3444 %ipeline


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7a!ard

! Di+ider is not )ull( pipelined structural hazard


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7a!ard

! nstructions ha+e +ar(in" runnin"times6 ma(be ;1 re"ister &rite in ac(cle < structural hazard


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7a!ard

! nstructions no lon"er reach =B inorder Write after write W!W" hazard


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7a!ard

! nstructions ma( complete in adi))erent order than the( &ere issued exceptions


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7a!ard

! >on"er latenc( o) operations #orefre$uent stalls for %!W hazards


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RA 7a!ards


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Structural 7a!ards


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Structural 7a!ards

! nterlock Detection! ethod 1: track the use o) the &rite

port in the D sta"e and stall aninstruction be)ore it issues:: a shi)t re"ister tracks &hen alread(<issued instructions &ill use the re"ister)ile* i) the instruction in D is needs to usethe re"ister )ile at the same time6 stall


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Structural 7a!ards

! nterlock Detection! ethod : stall a con)lictin" instruction

&hen it tries to enter , /=B:: could stall either issuin" or issued one* "i+e priorit( to the unit &ith the lon"estlatenc(*#ore co#plicated : stall arises )rom, /=B


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A 7a!ards

! ) >.D &ere issued one c(cle earlier! >.D &ould &rite $ one c(cle earlier than

ADD.D W!W hazard what if another instruction using F& 'etween

the#( ))) *o W!W


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7a!ard -etection in I-

! 1. ?heck )or structural ha!ards&ait until the re uired )unctional unit isnot bus( 7onl( )or di+ides9*make sure the re"ister &rite port isa+ailable &hen it &ill be needed*


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! . ?heck )or RA data ha!ards&ait until source re"isters are a+ailable&hen needed


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! . ?heck )or A data ha!ardsdetermine i) an( instruction in A1 A36D6 1< has the same re"isterdestination as this instruction*i) so6 stall the issue o) the instr in D


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,or8arding

! Ceneralized &ith more sources,-/ , 6 A3/ , 6 / , 6 D/ , 6, /=B


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*ut$o%$order 'ompletion

! ADD and 2 B complete be)ore D E! ut


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*ut$o%$order 'ompletion

0o& to deal &ith out


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*utline


! %2 R3444 %ipeline


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All in MIPS R4000


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MIPS R4000

! 5


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MIPS R4000

! I,: )irst hal) o) instruction )etch*%? selection*initiation o) instruction cache access*


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MIPS R4000

! IS: s econd hal) o) instruction )etch*completion o) instruction cache access*


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MIPS R4000

! R,:instruction decode and re"ister )etch*

hazard checkin"*instruction cache hit detection*


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MIPS R4000

! . : e8ecutione))ecti+e address calculation*

A> operation*branch


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MIPS R4000

! -,: data )etch)irst hal) o) data access*


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MIPS R4000

! -S: s econd hal) o) data )etchcompletion o) data cache access*


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MIPS R4000

! 9': ta" checkdetermine &hether the data cacheaccess hit*


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MIPS R4000

! 1: &rite back)or loads and re"ister


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!


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MIPS R4000

!


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MIPS R4000

!


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MIPS R4000

! $or&ardin"A> / , or , /=B


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MIPS R4000

! $% %ipeline! $% unit &ith three )unctional units:

$% di+ider6 $% multiplier6 $% adder! c(cles to 11 c(cles


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MIPS R4000

! $% unit &ith ei"ht di))erent sta"es


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MIPS R4000

! $% operations: latenc( and initiationinter+al


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MIPS R4000

! $% operations ,8ample 1$% multipl( G $% add


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MIPS R4000

! $% operations ,8ample $% add G $% multipl(


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MIPS R4000

! $% operations ,8ample : di+ide G add


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MIPS R4000

! $% operations ,8ample 3$% add G $% di+ide


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lec06-pipelining-mips.ppt