Omega test report

OMEGA PROJECT : Validation test report

ref.: XXXXX 1 /398 XXX Issue 1

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TEST REPORT

(OMEGA PROJECT)

project n° 28599





Reference : / 99 Date :

Issue : 01

Written by : EMC group Visa :

Approved by : Ph. BOITEUX Visa :

REVIEW CONTENTS





Edition Date Description Modifications

01

XXXXX New document File









REFERENCE’S DOCUMENTS

Reference Title Origin









CONTENTS

1. PURPOSE ........................................................................................................................................ 11

2. RECALL OF THE VALIDATION OBJECTIVES ....................................................................................... 12

3. RECALL OF THE USER'S REQUIREMENTS TO BE VALIDATED ............................................................ 13

4. VALIDATION PROCESS .................................................................................................................... 14

4.1 TESTING EQUIPMENTS .................................................................................................................. 14

4.2 VALIDATION ON A STAND ALONE CPU CARD...................................................................................... 14

4.2.1 Aims to be achieved .......................................................................................................... 14

4.2.2 Test points ........................................................................................................................ 14

4.2.3 Synthesis of Results acquired with a normally routed CPU board ...................................... 16

4.2.4 Synthesis of Results acquired with a willingly degraded CPU board (TBC) ......................... 33

4.2.5 Conclusion ........................................................................................................................ 33

4.3 VALIDATION ON A MULTIBOARD SYSTEM........................................................................................... 35


4.3.2 Simulation configurations .............................................. Errore. Il segnalibro non è definito.

4.3.3 Net tested ......................................................................................................................... 35

4.3.4 Synthesis of Results acquired with a normally backplane .................................................. 37

4.3.5 Synthesis of Results acquired with a degraded backplane ................................................. 46

4.3.6 Optimisation of the design ................................................................................................ 48

4.3.7 Conclusion ........................................................................................................................ 50

4.4 SIMULATION OF THE RADIATED EMISSION OF A BREADBOARD ............................................................... 52






4.4.2 Functional configurations ................................................................................................. 52

4.4.3 Test fixture ........................................................................................................................ 55

4.4.4 Comparison between simulations result and measurements ............................................. 56

4.4.5 Conclusion ........................................................................................................................ 59

4.5 VALIDATION OF MASK DEFINITION AND ASSIGNMENT REQUIREMENT ..................................................... 60

4.6 VALIDATION OF THE QUICK FILE AUTOMATIC TRANSMISSION ................................................................ 61

5. PCB DESIGN METHODOLOGY.......................................................................................................... 63

5.1 CURRENT STATUS OF A PCB DESIGN PROCESS .................................................................................... 63

5.2 INTEGRATION OF THE SIMULATION TOOL .......................................................................................... 63

5.2.1 Diagram of a design flow after integration of the simulation tool ..................................... 64

5.2.2 Engineering design phase ................................................................................................. 65

5.2.3 CAD (Computer Aided Design) phase................................................................................. 67

5.3 SIGNIFICANT BENEFITS OF THE TOOL ................................................................................................ 69

5.3.1 Benefits at Pre-layout phase ............................................................................................. 71

5.3.2 Benefits at Layout phase ................................................................................................... 71

5.3.3 Benefits at Post-layout phase ............................................................................................ 73

5.3.4 Saving of time estimated .................................................................................................. 75

6. LIMITATIONS TO BE IMPROVED IN THE SIMULATION ..................................................................... 78

6.1 RADIATED EMISSION SIMULATION ................................................................................................... 78

6.2 COMPONENT MODEL PARAMETERS .................................................................................................. 78

6.3 PRE-LAYOUT ANALYSIS OPTION ....................................................................................................... 78





7. ANNEXE : ....................................................................................................................................... 79

SYNTHESIS OF RESULTS ACQUIRED WITH A NORMALLY ROUTED CPU BOARD...................................... 79

7.1 SIGNAL INTEGRITY CHECK .............................................................................................................. 80

7.1.1 Clock signal ....................................................................................................................... 80

7.1.2 Control signal nets .......................................................................................................... 106

7.1.3 Data and address signal nets .......................................................................................... 126

7.2 NOISE ON VCC PLAN .................................................................................................................. 148

7.3 NOISE ON GROUND PLAN ............................................................................................................ 164

8. ANNEXE : ...................................................................................................................................... 176

SYNTHETIS OF RESULTS ACQUIRED WITH A MULTIBOARD SYSTEM .................................................... 176

8.1 CONFIGURATION WITH A CPU BOARD AND AN IO BOARD INTERCONNECTED THROUGH A BACKPLANE

NORMALLY ROUTED .................................................................................................................................. 177

8.1.1 Signal integrity check ...................................................................................................... 179

8.1.2 Noise on the backplane logical ground ........................................................................... 372

8.2 CONFIGURATION WITH A CPU BOARD AND AN IO BOARD INTERCONNECTED THROUGH A BACKPLANE

WILLINGLY DEGRADED............................................................................................................................... 264





ABREVIATIONS LIST

BMC Backplane Mother Board

CAD Computer Aided Design

EMC ElectroMagnetic Compatibility

EMIR EMIssion Radiated

GUI Graphic User Interface

HDT High Design Technology

IBIS Input/output Buffer Information Specification

OMEGA Optimisation of Multi board systems under Emc Guidelines for Avionics

PCB Printed Circuit Board

PRESTO Post-layout Rapid Exhaustive Simulation and Test of Operation

SSN Simultaneous Switching Noise

SCSB Standard Computer System Bus

TDR Time Domain Reflectometer

XTALK traces cross-TALK

Xsection Cross section





1. Purpose

This document is the final tests report which is owed in the framework of the project OMEGA and which

closes the task 4.

It presents the philosophy of the validation test, all the results analysis details and the investigation led

to understand the differences between simulations and experiments.





2. Recall of the validation objectives

The main objective of this validation :

is to test the PRESTO_MBMS V1.1 tool functional features through the users requirements

retained for the task 4 of the Omega project and presented in the document referenced

399.0026/99.

to verify and to evaluate the capability of the tool to improve a PCB design (changes in the

layout design or changes in component values) by means of a what-if analysis

The philosophy of PRESTO_MBMS V1.1 validation is essentially based on the comparison between

simulation results and lab measurements. Mismatched results (differences between the two results) are

investigated and if necessary, the validation test is carried on with interactive modifications between

simulations and experiments.

The different phases followed during this validation plan are :

Phase 1 : Simulations and lab measurements on PCB cards routed with avionics rules.

This validation test is performed on a single CPU card and on a multi-board

system made up of a CPU card and a I/O cards interconnected through a

backplane (BMC).

Phase 2 : Simulations and lab measurements on PCB cards willingly degraded. This

validation test is performed on a single willingly degraded CPU card and on a

multi-board system made up of a CPU and a I/O cards interconnected

through a willingly degraded backplane (BMC).

Phase 3 : Optimisation of the degraded card design

Phase 4 : This phase is specific to the radiation simulations and measurements carried

out on a single bread board





3. Recall of the user's requirements to be validated

The User’s requirements validated during the task 4 of the OMEGA project are the following ones :

1. Simulation of interconnected boards

2. Automatic transmission from a QUICKSIM ASCII file into PRESTO and BIDIR/Tristate

interfaces management

3. Mask definition and assignment

4. Noise on ground and power planes (planes modelling)

5. PCB modelling : 6 signals layers between two planes

6. radiated emission of a PCB





4. Validation process

4.1 Testing equipments

Specific avionics test benches and software are used to test the functionality of the different pcbs

(single CPU pcb or multiboard system).

In addition to this, a software has been specially developed so as to have the same functional

configurations between lab measurements and simulations : same data flow sense or same

percentage of simultaneous switching drivers.

All measurements are performed in the time domain by means of sample numerical oscilloscopes

with a bandwidth greater than 400 Mhz.

Differential active probes are used to pick-up the waveforms on the different test points

previously identified

4.2 Validation on a stand alone CPU card

4.2.1 Aims to be achieved

Validation of the following requirements :

non perfect planes modelling for inner voltages and SSN computation (noises on ground

and power planes)

bi-directional interfaces management

Coherence between simulation results and lab measurements related to :

clock net signal integrity

control net (RD_FLASH, CS_FLASH, OE_RAM, RW), data and address bus signal integrity

noises on Vcc and ground planes

Verification of the tool capability to improve the degraded CPU card design by optimising the

decoupling capacitor values

4.2.2 Test points

The reference of the test points (component pin-out, capacitor or resistor) are presented on each graph.

Simulations and measured waveforms are visualised at the following points of the board .

For signal integrity





- at each end of clock signal nets

- at each end of control, data and address signal nets

For noise on power and ground planes

- either between the two nodes of a decoupling capacitor or between the Vcc and Ground

nodes of a given component (micro-processor, buffers, RAM or clock generator)

- between two points of the CPU logical ground to evaluate the non perfect ground effects on

the noise level





4.2.3 Synthesis of Results acquired with a normally routed CPU board

The details of the comparison results between simulation and measurements are presented in Annex 7 :

§ 7.1 page 80 : signal integrity check

§ 7.2 page 148 : noise on Vcc plan

§ 7.3 page 164 : noise on Ground plan

4.2.3.1 signal integrity check

The graphs are presented § 7.1 page 80 and are completed by the following tables which compare the

different parameter values got by simulation and measurements.

To compare the simulation results to the measure, the following acceptance criteria are used including

different type of errors (measurements, simulation, analysis...) :

on rise and fall time value, the difference (diff (%) ) shall be less than 20%

on signal amplitude value, the difference (diff (V) ) shall be less than 0.3 V

From the comparison results analysis, the following observations can be drawn :

- There are appreciable differences between simulation and measurement on rise time and fall

time values (see following tables)

- The line reflections and the oscillations sur-imposed on the signal are very different in some

cases (ex : CLK40_RAM and CLK40_FLASH nets in annex 7 § b) page 88 and § c) page 96)

- simulation results are very close to the measurement ones when the signal frequency is low

(ex : CLK20 net and CLK40_RAM net in annex 7 § a) page 80 and § b) page 88).

- the differences between simulations and measurements are particularly highlighted with high

frequency signals (ex : CLK40_RAM and CLK40_FLASH nets in annex 7 paragraph b) page 88

and paragraph c) page 96)) and specially on the line reflections.





a) Clock signal

Signal

name

Test

point

Ref

page

Tr (ns) Tf (ns) Rise Edge Overshoot (V) Fall Edge Overshoot (V) Amplitude (V) Reflection

Oscilation Simul Meas diff (%) Simul Meas. diff (%) Simul Meas diff (V) Simul Meas. diff (V) Simul Meas diff

(V)

CLK20

IC72-11 80 ? 2.6 ? 1.2 3.8 3.8 0 -0.5 -0.4 0.1 3.8 3.8 found

R1048-2 80 1.8 2.6 31 1.38 1.4 1.4 4 3.9 -0.1 -0.5 -0.4 0.1 3.8 3.8 found

IC195-154 80 0.93 2.1 56 0.6 1 40 4.1 3.8 -0.3 -1.1 -0.7 0.4 3.9 3.8 found

CLK40-

RAM

IC72-19 88 ? 3.8 ? 2 5.1 4.6 -0.5 ? -0.6 ? 4.4 different

IC163-89 88 0.8 2.2 64 0.4 1.2 67 5.4 4.6 -0.8 -2 -1.4 0.6 ? 4.5 different

IC162-89 88 0.9 2 55 0.6 1.1 45 5.3 4.6 -0.7 -2.6 -1.4 1.2

?

4.5 different at

signal top level

CLK40-

FLASH

IC72-23 96 ? 7.39 ? 4.15 ? 5.2 0 different

IC155-29 96 3 3.3 9 2.6 2.31 -13 4.6 4.7 0.1 -0.9 -0.8 0.1 ? 4.5 slightly

different at

signal top level

IC158-29 96 3.9 3.46 -13 3 2.56 -17 4.7 4.7 0 -1 -0.8 0.2 ? 4.7 different at

signal top level





? : can't be estimated (not found in the .wave file)

appreciable differences between simulation and measurement





b) Control signal

Signal

name

Test

point

Ref

page


Oscilation Simul Meas diff (%) Simul Meas. diff (%) Simul Meas diff (V) Simul Meas. diff (V) Simul Meas diff

(V)

CS FLASH IC154 - 2 106 24 11.6 -107 7.5 5.3 -42 3.2 3.2 0 -0.5 -0.3 0.2 3.2 3.2 0 found

IC195 - 53 106 X X 3.2 3.2 0 -0.3 -0.2 0.1 3.2 3.2 0 found

Read

FLASH

IC157 - 54 106 12.7 9.5 -34 2.6 1.8 -44 3.4 3.2 -0.2 -0.8 -0.5 0.3 3.3 3.2 -0.1

slightly

different at

signal top level

IC161 - 54 106 12.6 X 2.1 X 3.5 3.2 -0.3 -0.8 -0.6 0.2 3.3 3.2 -0.1 different at

signal top level

IC195 - 26 106 3.3 3.2 -0.1 -0.3 -0.2 0.1 3.2 3.2 0 found

OE RAM IC163 - 86 120 5.6 5.5 -2 1.3 1.6 19 3.3 3.2 -0.1 -0.8 -0.5 0.3 3.3 3.2 -0.1 found

RW IC163 - 87 120 5.6 4.5 -24 1.6 1.6 0 3.3 3.2 -0.1 -0.8 -0.5 0.3 3.3 3.2 -0.1 found






X : not measured






c) Data and address signal

Signal

name

Test

point

Ref

page


Oscilation Simul Meas diff (%) Simul Meas. diff (%) Simul Meas diff (V) Simul Meas. diff (V) Simul Meas. diff

(V)

A_F1 IC195 - 120 126 ? 13.3 ? 7.6 3.2 3 -0.2 -0.3 -0.1 0.2 3.2 3 -0.2 found

IC154 - 28 126 ? 9.16 ? 2.68 3.2 3 -0.2 -0.7 -0.4 0.3 3.2 3 -0.2 Slightly

different

Address

bus

IC154 - 26 126 ? 4.17 ? 3.47 3.4 3.1 -0.3 -0.7 0 0.7 3.3 3.1 -0.2 different

IC181 - 52 126 ? 4.7 ? 3.8 3.4 3 -0.4 -0.2 0 0.2 3.3 3 -0.3 different

IC181 - 5 126 ? 5.7 ? 5.4 3.8 3.6 -0.2 -0.5 -0.4 0.1 3.3 3.1 -0.2 found

IC194 - 319 126 ? 7.7 ? 7.6 3.3 3.2 -0.1 -0.1 -0.1 0 3.2 3.1 -0.1 found


X : not measured






d) Investigations

The differences noted between simulation and measurement results are though to be due :

- to the model of components used in the simulation and which is not representative of the

real case (ex : package and RLC bonding parameters, default models used for component

not modelled...) and which can leads to an excess of amount of capacitor on the net

- to the way the tool uses the IBIS models V(t) ramp parameters (rise and fall time...) which

are generally associated to a load circuit depending on the technology of the buffer (ex :

500 Ohms / 30pF)

These different factors could explain some appreciable differences noted between simulation

results and measurements. The results obtained on the net CLK40_FLASH is used for

investigation.

At the signal top level

- When we compare the results of Figure 4-1 page 25, the signal waveform seems to be

very different in a first approach. But when we analyse the result, we can note that this

difference is due to the value of the rise time simulated (12ns) which is greater than the

measured one ( 9ns).

The consequence is that on a signal pulse width of 17 ns, it remains no sufficient time (5

ns including the signal fall time instead of 8 ns) to show the line reflection simulated by

the tool.

This difference of 3ns corresponds approximately to the half period of the reflection wave

(3.5 ns)

- To highlight the impact of the rise time on the signal wave shape, the test on the pentium

board has been performed on the same net with a lower frequency (24 Mhz). The results

are presented on Figure 4-2 page 26

The simulation seems to be more representative of the measurement. The only difference

is that the pulse width is more important (the oscillation sur-imposed on the signal are

represented) and the impact of the rise become less important. However, it shall be noted

that a half period of the reflection wave is missing (2 oscillations at the signal top level

instead of 3 measured).

At the signal low level





The multiple oscillations present at the signal low level seem to be due to the component and

the ground plane models. There is a resonance At 32 Mhz which is not present at 24 Mhz (see

Figure 4-2 page 26)





CLK40_flash simulation : IC 72 pin 23

(clock frequency : 32 Mhz)

CLK40_flash measurement : IC 72 pin 23


12 ns

5 ns





Figure 4-1 : comparison between simulation and measurement results at CLK40_FLASH driver output



9 ns

8 ns





Figure 4-2 : comparison between simulation and measurement results at CLK40_FLASH driver output

(signal frequency : 24 Mhz)



12 ns 10 ns

9 ns 13 ns





4.2.3.2 Noise on Vcc power plane

The graphs are presented § 7.2 page 148 .

The measurement is performed with an active probe between the two nodes of a 5V decoupling

capacitor or between the Vcc and Ground nodes of noisy components selected on the board as micro

controller and buffers.

For measurement with functional activity on the CPU board, this activity consist in a reading of a data

in RAM memories with a repetitive cycle of 1 µs. It shall be noted that between the reading cycle, the

CPU goes on with its own instructions.

a) Comparison results

On 5Vcc plane :

It is not possible to compare the simulation result to the measurement due to the switching

frequency of the DC/DC converter on the pentium board

This case is presented in § 7.2 c) page 162. As the noise sources are not only generated by the

switching of the I/O outputs, it is not easy to compare the simulation results to the measure

in terms of noise spectrum and amplitude

On 2.5 Vcc and 3.3 Vcc planes

Simulation 2.5 V planes 3.3 V planes

Configuration

differential mode simulation

IC194-19 (Vcc) and

IC194-1 (Gnd)

IC194-223 (Vcc) and

IC194-321 (Gnd )

IC178-7 (Vcc) and

IC178-11 (Gnd)

n° 1 only CLK nets plane model

50:1 25 mV pp 18 mV pp 80 mV pp

n° 2 all CLK + all

address (A_xx)+

Ram control nets

(CS-OE)

plane model

50:1 80 mV pp 63 mV pp 180 mV pp





n° 3 all nets selected plane model

50:1 180 mV pp 200 mV pp 900 mV pp

Measurements 2.5 V planes 3.3 V planes

Configuration between IC194-19

(Vcc) and IC194-1

(Gnd)

between IC194-223

(Vcc) and IC194-321

(Gnd)

between IC178-7 (Vcc)

and IC178-11 (Gnd)

n° 1 with reduced activity 30 mV pp 4 mV pp 20 mV pp

n° 2 with functional activity 100 mV pp 80 mV pp 400 mV pp





b) Comments

It is difficult to compare the simulation results to the measurements to the extent that the real

internal activity of the micro processor is not well known and has a great impact on the noise spectra

(see graphs at § 7.2 a) page 150 and § 7.2 b) page 154 in functional activity configuration). We can

see on these graphs the soft routine frequency and its harmonics (ex: 2.5 VCC at pin IC194-223 ).

Nevertheless, the simulation results show the general trend of the noise level seen in measurements

:

The 2.5 V plane is more polluted than the 3.3 Vcc plane around IC 194

The area of the 3.3 Vcc plane around IC194-223 is less disturbed than the area of the 3.3 Vcc

plane around IC178-50

The order of magnitude of the noise level is comparable





4.2.3.3 Noise on GND power plane

The test points and the related graphs are presented in annex 7 § 7.3 page 164. The points are

selected in order to have a zoning of the ground plane noise.

The measurement is performed with a functional activity on the CPU board, this activity consist in a

reading of a data in RAM memories with a repetitive cycle of 1 µs.

In the simulation, this configuration with a repetitive 1µs cycle wasn’t used. The driver switching

frequency wasn’t a multiple of the main frequency clock frequency with a 50% duty cycle. The

objective is to compare the peak-to-peak noise level induced in the ground impedance

An active probe is used to measure the ground noise between the nodes selected

a) Comparison results

SIMULATION GND plane wave shape noise level

Configuration

differential mode simulation

C66 – C361 C63 – C66 C63 – C311 C63 – C64 C313 – C157 C66 – C243

n° 1

all CLK + all

address

(A_xx)+ Ram

control nets

(CS-OE)

plane model

50:1 22 mVpp 34 mVpp 26 mVpp 28 mVpp 14 mVpp 35 mVpp

n° 2 all nets plane model

50:1 192

mVpp

315

mVpp

128

mVpp

X 70 mVpp 224

mVpp





MEASUREMENT GND plane wave shape noise level

(Max peak-to-peak level)

Configuration

differential mode measurement

C66 – C361 C63 – C66 C63 – C311 C63 – C64 C313 – C157 C66 – C243

n° 1 read Ram memories

configuration 80 mVpp 325

mVpp

50 mVpp 70 mVpp 60 mVpp 140

mVpp





b) Comments

The ground noise level simulated does not match the measured one. In the same configuration

(read Ram memories configuration), the simulation shows a peak-to-peak noise level lower than

the measure.

the differences between the simulation and the measurement are too important and it seems

that the way the planes are modelled have a non negligible impact on the simulation result

accuracy.

The simulation results which give significant results compared to the measure ones are the

simulation with all nets. It can be noted that the general trend of the noise level on the ground

plane is given by the simulation.

c) remark

It shall be noted that all on the simulation result acquired in the time window from 4µs to 5µs (ex :

see graph in §7.3 f) page 174 ) show a spike which can not be explained with the functional activity

of the pentium board...





4.2.4 Synthesis of Results acquired with a willingly degraded CPU board (TBC)

The decoupling capacitor of noisy components (definir le composant) have been reduced from (donner

la valeur initiale) to a value of (donner la valeur finale) in order to induce significant noise on the power

distribution rails. The admissible value has been determined by simulation .

The simulations and the measurements have been performed in the worst case configuration previously

determined ( 100 %data drivers simultaneous commutation).

The results are presented below :

a) noise on Vcc net

simulation and measurements

comparison between lab and simulation

b) noise on the logical ground



c) clock signal integrity



4.2.5 Conclusion

a) User's requirements validation

"non perfect planes modelling" and "bidir management" requirements are compliant to what

have been specified by the user

b) Coherence between simulation results and lab measurements related to :

Clock net signal integrity





The analysis of the results shows good coherence between measurements and simulation.

However the representativeness of the component models used has a great impact on the

accuracy of the simulation, specially on rise and fall times or on line reflection. This is

particularly apparent on high frequency signals (> 40 Mhz)

Non perfect planes modelling for inner voltages and SSN computation

Noises on power planes

The simulation results show the general trend of the noise level seen in

measurements. The order of magnitude of the noise level is comparable although it

is difficult to simulate the real internal activity of the micro processor

Noises on ground planes

In a similar configuration, The order of magnitude of the noise level is not

comparable : the simulation results show a level of noise clearly less important than

the measure. It seems that the model used for the ground plane has a great impact

on the simulation accuracy

c) Verification of the tool capability to improve the degraded CPU card design by optimising the

decoupling capacitor values





4.3 Validation on a multiboard system


a) Validation of the following requirements :

possibility to perform simulation with several board interconnected

noises on the ground plane (non perfect planes modelling for SSN computation)

PCB modelling : 6 signals layers between two planes

b) Coherence between simulation results and lab measurements related to :

signal integrity with SSN and cross-talk disturbances

noise on the back-plane ground with SSN cross-talk disturbances

c) Verification of the tool capability to improve the degraded back-plane design by optimising

ground net layout

4.3.2 Net tested

Simulations and measured waveforms are firstly performed on the critical nets of the SCSB bus detected

by the cross talk coupling conditions and secondly on the backplane logical ground net. All the

measurements have been made at the interface of the CPU connector (J71), IO1 connector (J82), IO2

connector (J92), SPARE connector (J102)

a) Signal integrity controlled at the inputs of the SCSB bus receivers at I/O card connector level.

clock net : CLK_L2

control signal : REQ_L2, RDY_L2

data and address bus :SCSB_AD(0),SCSB_AD(12),SCSB_AD(22),

SCSB_AD(35)

b) between two points of the logical ground of the mother board : the differential voltage

markers will be set between a ground pin of the CPU connector and a ground pin of the IO

connector :





J81-B6 (IO1) and J71-B6 (CPU);


J101-B6 (SPARE) and J91-B6 (CPU);







J71-B6 (CPU) and J72-B8 (CPU)





4.3.3 Synthesis of Results acquired with a normally backplane

The results can be viewed on annex 8.1 page 177.

The first version of the multiboard tool does not include the waveform postprocessor option used on the

single board. So it’s not possible today to present a result comparative board between simulation and

measurements on the signal integrity parameters : trise/tfall time, overshoot and undershoot levels.

The comparison is only based on the different curves obtained in simulation and in lab measurements.

4.3.3.1 Control signal integrity check

It can be noted on the graphs presented in annex 8.1.1.1 page 179 that the simulation results match the

measurements with a good approximation:

the oscillations and the line reflections on the signal are found

the fall edge and rise edge overshoot amplitude are similar

We can conclude that the signal integrity of the control nets is well simulated by the tool.

Examples are given Figure 4-3 and Figure 4-4.

4.3.3.2 Adress/data signal integrity check

The results are presented in § 8.1.1.2 page 218.

From the comparison results analysis, the following observations can be drawn :

there are appreciable differences between simulation and measurement on rise and fall time

the line reflections and the oscillations sur-imposed on the signal are very different

Examples are given Figure 4-5 and Figure 4-6 to emphasise these differences.

4.3.3.3 Observation

Note that the signal controls and data/address bus are not driven by the same component. The control

signal are driven by an Actel component (A42MX16) for the REQ_L2 signal and by buffer component

(74ALVCH162260) for data/address bus.





The difference noticed should became from the component models used for the simulation.





measurement on REQ_L2 : J72-C2

simulation on REQ_L2 : J72-C2





Figure 4-3: Comparison between simulation and measurement on REQ_L2 signal











Figure 4-4: Comparison between simulation and measurement on tfall for REQ_L2 signal

simulation on SCSB_AD(12) : J71-A5





Figure 4-5: Comparison between simulation and measurement on SCSB_AD(12) signal

measurement on SCSB_AD(12) : J71-A5











Figure 4-6: Comparison between simulation and measurement on tfall for SCSB_AD(12) signal





4.3.4 Synthesis of Results acquired with a degraded backplane

The bakcplane has been willingly degraded as follow :

The clock traces is not buried between 2 ground planes

The ground net is routed by means of an area filled trace less than 1mm in width.

The nets RDY_L2 and REQ_L2 are routed as closed as possible with the clock net CLK_L2 in

parallel straight traces.

The simulations and the measurements are presented in § 8.2 page 264

The results are presented below :

a) noise on the backplane logical ground



b) signal integrity on clock nets at CPU level (entrée connecteur + carte : donner le cas le plus

intéressant)



c) signal integrity on clock nets at IO level (entrée connecteur + carte : donner le cas le plus

intéressant)



d) signal integrity on control signal nets at CPU level (entrée connecteur + carte : donner le cas le

plus intéressant)



e) signal integrity on control signal nets at IO level (entrée connecteur + carte : donner le cas le

plus intéressant)







f) signal integrity on SCSB data and address nets at CPU level (entrée connecteur + carte : donner

le cas le plus intéressant)



g) signal integrity on SCSB data and address nets at IO level (entrée connecteur + carte : donner








4.3.5 Optimisation of the design

The tool has been used to determine the impacts of the backplane ground net modifications on the

signal integrity.

The simulations are performed in the worst case configuration previously determined (100 % data

drivers simultaneous commutation).

4.3.5.1 Simulations results with a ground defined as an ideal plane


simulation and measurements (mesures obtenues au § Errore. L'origine riferimento non

è stata trovata.)


b) signal integrity on clock nets at CPU level (entrée connecteur ou carte : donner le cas le plus

intéressant)


è stata trovata.)


c) signal integrity on clock nets at IO level (entrée connecteur ou carte : donner le cas le plus

intéressant)


è stata trovata.)


d) signal integrity on control signal nets at CPU level (entrée connecteur ou carte : donner le cas

le plus intéressant)


è stata trovata.)


e) signal integrity on control signal nets at IO level (entrée connecteur ou carte : donner le cas le

plus intéressant)






è stata trovata.)










4.3.5.2 Simulations results with the ground net defined as a non perfect plane



è stata trovata.)


b) signal integrity on clock nets at CPU level (entrée connecteur ou carte : donner le cas le plus

intéressant)


è stata trovata.)






c) signal integrity on clock nets at IO level (entrée connecteur ou carte : donner le cas le plus

intéressant)


è stata trovata.)


d) signal integrity on control signal nets at CPU level (entrée connecteur ou carte : donner le cas

le plus intéressant)


è stata trovata.)


e) signal integrity on control signal nets at IO level (entrée connecteur ou carte : donner le cas le

plus intéressant)


è stata trovata.)










4.3.6 Conclusion

a) Coherence between simulation results and lab measurements related to :

signal integrity including SSN and cross talk disturbances noises





noises on backplane ground plane (non perfect planes modelling )

b) Verification of the tool capability to improve the degraded backplane ground layout design





4.4 Simulation of the radiated emission of a breadboard

The test support used for this validation is a breadboard specially developed and including a micro-

controller.

The measurement is performed in a semi-anechoid chamber with :

a whip antenna in the frequency range from 100 Khz to 30 Mhz

a bicolog antenna in the frequency range from 30 Mhz to 1Ghz


Validation of the tool capability to predict the radiated emissions of a non complex PCB.

4.4.2 Functional configurations

Two running functional modes have been used to activate the I/O ports of the micro-controller.

a) Load configuration

In this configuration, each output of the port B drives a capacitance load of 50 pF.

The 8 outputs of this port are switched simultaneously according to the following bit sequences :

4 cycles with 400 ns time duration and 50 % duty cycle

a fifth cycle with (500ns + 200ns) time duration

PB0

PB7

50 pF

50 pF

µcontroller





the total soft routine duration is equal to 2300 ns

200 ns

1 2 3 4 5

2.5 Mhz / 400ns 500 ns

2300 ns





b) BUFFER configuration

In this configuration, ports T and J of the micro controller drive the inputs of a buffer type

FCT16543.

The outputs of port T (or port J) are switched simultaneously according to the following bit sequences

:

4 cycles with 816 ns time duration and 50 % duty cycle

a fifth cycle with (702 ns + 408 ns) time duration

the total soft routine duration is equal to 4374 ns

A delay of 200 ns is inserted between the simultaneous commutation of the outputs of port T and the

simultaneous commutation of the outputs of port J

PT0

PT7

µcontroller

PJ0

PJ7

FCT16543

408 ns

1 2 3 4 5

1,225 Mhz / 816 ns 702 ns

4374 ns

200 ns

Port T

Port J

delay





4.4.3 Test fixture

The test fixtures for radiated emission measurements are described in the following figure. The

measurement is performed for each rotation of the PCB around its radial axis

* the copper plan is connected to the mechanical ground

1m

UUT shielded box

copper plan *

1m

10 cm

antennae

semi anechoid chamber





4.4.4 Comparison between simulations result and measurements

4.4.4.1 LOAD configuration

Example of measurement results in load configuration

* 430 Khz and its harmonics are related to the soft routine cycle

* 2,5 Mhz and its harmonics are related to the port B outputs switching frequency

Corresponding simulation result

0

10

20

30

40

Level [dBµV/m]

30M 40M 50M 70M 100M 200M 300M 400M 600M 1G

Frequency [Hz]

measure with a bicolog antenna

0

10

20

30

40

Level [dBµV/m]

150k 300k 500k 1M 2M 3M 4M 5M 7M 10M 30M

Frequency [Hz]

measure with a whip antenna

430 khz

2.5 Mhz









4.4.4.2 BUFFER configuration

Example of measurement results in buffer configuration

* 230 Khz and its harmonics are related to the soft routine cycle

* 1,225 Mhz and its harmonics are related to the port T J outputs switching frequency

Corresponding simulation result

0

10

20

30

40

Level [dBµV/m]

30M 40M 50M 70M 100M 200M 300M 400M 600M 1G

Frequency [Hz]

0

10

20

30

40

Level [dBµV/m]

150k 300k 500k 1M 2M 3M 4M 5M 7M 10M 30M

Frequency [Hz]

1,225 Mhz

230 Khz

measure with a whip antenna measure with a bicolog antenna





4.4.5 Conclusion

The result analysis show outstanding differences between measurement and simulation :

at low frequency (< 30 Mhz), we can noted the lack of frequency rays above 0 dbµV/m with the

simulation when the measurement reveal the switching frequency of the outputs and the routine

loop frequency with a consequent level above the noise.

at high frequency ( > 30 Mhz), the wave shape of the radiation spectrum are not comparable

these differences are though to be due to :

the assumption of being in far field conditions is not respected with the electromagnetic

formulation. The tool is only able to perform radiated simulation for far field (d>3m or f=30Mhz),

which are not compatible with Aeronautical CEM test conditions (d=1m and 10Khz<f<400Mhz).

the inability of the tools to simulate the radiated emission from multi-clock signals

the impact of the broadband noises on the spectrum radiation





4.5 Validation of Mask definition and assignment requirement





4.6 Validation of the Quick file automatic transmission

4.6.1 Description

The file which describe the simulation waveforms is a .log format file.

This file is converted by the tool in an interpretable format by Presto.

The flow is described below

4.6.2 Results

.log

file

.qseq

file

QUICKSIM TRANSLATOR

Simulation waveforms

The Quicksim sequence is

translated in a Presto

sequence, .qseq file

QUICKSIM SELECTOR

allows selection net for

simulation





The automatic transmission of a Quiksim file flow runs correctly

We have done a go no go test on a clock signal, the Quicksim simulation waveform has been translated

and visualise on Sights (waveform viewer of Presto).

More test will be achieved subsequently.





5. PCB design methodology

5.1 Current status of a PCB design process

The EMC design manager operates in different phases of an avionics equipment design process :

at pre design step with functional architecture and technological choices in collaboration with

the electronic functional designer

at main design step with schematics analysis and EMC requirements writing

at physical PCB design step with component placing, layout and routing analysis and verification

of the taking into consideration of EMC constraints in collaboration with the PCB layout design

engineer

5.2 Integration of the simulation tool

The simulation tool is inserted in the existing design flow at PCB layout and routing phase and is applied

only on the numerical functional parts of the PCB

In the engineering design phase, the EMC manager will enquire about the availability of the EMC

models of all logical component used in the design. The creation of new EMC component models

(by component models provider) will be initialised in the same way as for models used in

numerical simulation

In CAD (computer aided design) phase, the CAD file extracted from the PCB layout is provided as

input data for simulation. This file will be stored in a specific directory in order to be used by the

EMC engineer without interrupting the PCB design progress. Therefore, the simulation will be

performed outside the design flow.

At the beginning of the CAD design phase, the EMC manager shall specify if the simulation tool

will be used or not according to the complexity of the PCB.

To limit the number of iterations between simulations and CAD data extraction, break points for

the generation of the cadif file will be defined in the PCB design flow by the EMC manager.

These break points will be determined in collaboration with the PCB layout designer .





5.2.1 Diagram of a design flow after integration of the simulation tool

The integration of PRESTO in AEROSPATIALE design methodology is described in the following bloc

diagram. The coloured blocs define the operations related to the use of the simulation tool in the

existing design process.





5.2.2 Engineering design phase

first list of components to be

modelled and developed for

simulation

- working frequency plan

- component pre nomenclature analysis

- electrical architecture definition

preliminary electrical design

detailed electrical design

additional list of components to

be modelled and developed for

simulation

functional simulations

yes

no

EMC, and component technology pre-

analysis selection

EMC protection pre assessment

- list of components

- schematics

yes

no

EMC and functional constraints for

CAD and PCB layout (NCC)

results analysis ?

results analysis ?

EMC analysis EMC design rule and

requirement

REQUIREMENTS

operational, technical and electrical

constraints

environment conditions (ex :

electromagnetic environment and

lightning requirements)









5.2.3 CAD (Computer Aided Design) phase

data transfer to PCB production

yes

no

component placing thermal simulations

yes

no control results

ok ?

PCB layout and routing

yes

no simulations results

ok?

Cadif file : extraction of

layout information's

physical PCB design control

layout and routing

signal segregation

cross-talk risks

etc...

yes

no non compliance accepted

?

simulation with PRESTO

evaluation of cross-talk coupled sections

verification of the integrity of critical signals (clock,

control, write and read, data and address bus)

what-if analysis

etc...

EMC requirement fulfilment controls

PCB zoning and component segregation

compliance with :

- trace length constraints

- decoupling capacitor constraints

- I/O component constraints

- etc...

control results

ok ?

compliance matrix related

to NCC constraints (DCC)









5.3 Significant benefits of the tool

5.3.1 in a PCB design process purpose

Signal-integrity, crosstalk, and EMC analysis are significant components of successful high-speed PCB

design particularly as IC switching speeds increase.

Taking them into consideration early in the design process allows the user to:

generate constraints for PCB router

avoid costly PCB turns

reduce time to market delay

ensure that timing budgets are met

produce higher-quality boards

avoid long lab sessions searching for intermittent failures

avoid embarrassing and costly test failures

However these benefits are not present at each design step of a PCB. The main steps followed by the

development of an avionic PCB are described below:

Pre-layout Layout Post layout





Board zoning

Component placing

critical nets routing

SI, Xtalk, EMC

analysis

Post layout EMC

verification

Full board placing

and routing

EMC and timing

pre-analysis

System design

Part selection

Schematic entry

functional and

EMC validation test

Prototype





5.3.1.1 Benefits at Pre-layout phase

PRESTO MBMS 1.0 is not a router and does not offer pre-layout analysis option, so Signal-integrity,

crosstalk and EMC analysis can not begin before the PCB is laid out. The saving of time is therefore

negligible at this step and the direct benefits expected are limited.

5.3.1.2 Benefits at Layout phase

The saving of time is negligible at this step.

However, the use of the tool at this stage will allow a better prediction of EMC problems on the PCB, will

bring appropriate solutions where it is less costly and more efficient and in fine it will give greatest

chances of producing a successful first-prototype board.

a) Best PCB design

With the simulation tool PRESTO MBMS 1.0, mistakes on the PCB will early be caught and over-

protected design or inadequate EMC solutions (which are generally expensive) will be avoided. This

will help us:

to correctly study the trade-offs between different routing topologies, board layer stackups

and even IC driving technologies before the full board is laid out.

to correctly examine the effects of grounded guard traces and to compare their usage in order

to increase trace separation

to optimally terminate transmission line for high speed signals

b) Accurate constraints for optimum reduction of coupling including :

minimum trace-to-trace separation

maximum parallel run lengths

maximum driver IC slew rate

stackup layer thickness and position





c) The tool PRESTO will give helpful assistance to find other types of problems that can only be found

after PCB layout. For example, even a properly designed net can be negatively affected by the layout

process, e.g., if the trace's length is not constrained properly during routing, or if a net wanders too

many times between board layers. Also, it is sometimes difficult to pre-plan nets beyond the truly

critical ones on a board.





5.3.1.3 Benefits at Post-layout phase

As the tool allows us to eliminate the EMC problems early in the design, we will be able to :

a) Enhance the old PCB design by anticipating the effects of technology changes earlier in the design

process or the emergence of new technologies with very high frequencies

b) Avoid costly PCB turns

Getting the PCB right the first time means a shorter design cycle and thus significant cost saving

c) Reduce budget overruns

Making design changes before prototypes are built, is far less costly than making changes after

fabrication and this limits budget overruns.

d) Produce higher-quality boards

The result is cleaner boards, reduced time in the lab test sessions, fewer PCB revisions, fewer

signal-quality, delay, crosstalk test failures and significantly lower product-development costs.

This increases the gain in productivity and the reduces the cost / performance ratio.

e) Reduce time to market delay

By getting the avionics card right the first time with a high quality will greatly reduce the time to

market delay.

f) Avoid long lab sessions searching for intermittent failures

The tool can be used for emergencies to pull us through a problem found in validation/integration

phase. The tool gives helpful assistance for investigation by let us trying several solutions quickly

and choosing the most appropriate one.

g) Avoid costly validation/qualification test failures

h) Reduce costly time consuming EMC test sessions for minor modifications

The only way today to suitable evaluate the potential EMC risk on electronic equipment or avionic

card and to check their compliance with EMC constraints is to perform EMC tests on a prototype.

This approach requires the development of a prototype and important EMC facilities which

unfortunately represents a costly investment for minor modifications or evolution on the card









5.3.1.4 Saving of time estimated

The save of time due to the use of PRESTO in our design flow is very appreciable at post layout phase

when the prototype undergoes all the tests necessary for it certification

Related to the time to market delay, the dead loss of time induced by EMC failures is estimated as follow

:

12% when the EMC failures occur at functional validation test phase

25% when the EMC failures occur at EMC validation test phase

30% when the EMC failures occur at EMC qualification test phase

For minor modifications or evolution in the design (new components, technology changes, etc...), the

save of time is estimated to 25 % specially due to the fact that PRESTO is used as a valuable EMC analysis

means which avoid costly re-validation and re-qualification tests.

From this analysis, we can say that the sooner the mistakes are caught, the less time and money are

spent : it costs many times more to fix a mistake after PCB layout than before, and another many times

more to fix it after prototyping than before. In terms of real total cost, the impact of EMC failures at post

layout phase is very important and can represent 30% of the final product.

Synthesis

Step benefits expected saving of time

Pre layout helpful assistance to generate routing

constraint (no pre layout analysis option in

PRESTO)

0%

Layout better PCB design

better prediction of EMC problems

0%

Post layout Anticipating the effects of technology

changes

avoid costly PCB turns

12% when the EMC failures occur at

functional validation test phase






reduce time to market delay

ensure that timing budgets are met

produce higher-quality boards

avoid long lab sessions searching for

intermittent failures

reduce costly time consuming EMC test

sessions for minor modifications

EMC validation test phase


EMC qualification test phase





5.3.2 In a research development purpose

To carry out EMC research studies on new high speed electronic designs or on PCB enhancement, it is

necessary up to now to develop a prototype card including the different functional configurations to be

analysed from the EMC viewpoint. This approach unfortunately represents a non negligible investment

cost for PCB manufacturing and components purchase.

With the simulation tool it shall be possible to perform the same EMC analysis on a virtual prototype

PCB and tis process based on a simulation approach will allow a great flexibility :

to study the trade-offs between different routing topologies

to anticipate the effects of technology changes or the emergence of new technologies with very

high frequencies

to accurately examine the effects of a transmission line ending impedance on the line reflection

to correctly reduce the coupling section between parallel traces

In fine, this will end by a better specification of EMC constraints for future PCB design





6. Limitations to be improved in the simulation

6.1 Radiated emission simulation

Moreover the limitations identified in the user’s requirement document (the striplines radiations

can’t be simulated), the tool is limited for far field simulation. It allows a simulation with antenna

distance d>3m and a signal frequency>30 Mhz. These conditions are not compatible with

Aeronautical EMC test specification (d=1m and spectral frequency range between 10Khz and

400Mhz).

6.2 component model parameters

models representativeness at high frequency : impact of trise/tfall parameters on signal integrity.

pin to pin connector model can’t be used with ground pins.

Ground plane modelling shall be more accurate to present a greater representativeness of the

results.

6.3 pre-layout analysis option

no pre layout option available in MBMS version.





7. ANNEXE :

Synthesis of Results acquired with a normally routed

CPU board





7.1 Signal Integrity check

7.1.1 Clock signal

a) Example 1: CLK20

Functional configuration

CLK20

IC72 IC195

A42MX16 ROBOCLOCK

11 154

CPU BOARD

R1048

27.4 2





simulation set up

no SSN

no Xtalk

no what-if analysis

tstart : 2000 ns

tstop : 2500 ns

resolution : 2048

planes modelled (10 : 1)

nets selected : only clock nets

comparison between simulation and measurements

See following curves





CLK 20 simulation : IC 72 pin 11

CLK 20 measurement : IC 72 pin 11









CLK 20 simulation : R1048-2

CLK 20 measurement : R1048-2









CLK 20 simulation : IC 195 pin 154

CLK 20 measurement : IC 195 pin 154









b) Example 2: CLK40_RAM


CLK40_RAM net

IC72

IC163

IC162

RAM

ROBOCLOCK

RAM

19

89

89

CPU BOARD





simulation set up

no SSN

no Xtalk

no what-if analysis

tstart : 2000 ns

tstop : 2500 ns

resolution : 2048









CLK40_RAM simulation : IC 72 pin 19

CLK40_RAM measurement : IC 72 pin 19





























c) Example 3 : CLK40_FLASH


CLK40_FLASH

29

IC154 FLASH memories

IC72

ROBOCLOCK

CPU BOARD

29

IC155

29

IC156

29

IC157

29

IC158

29

IC1549

29

IC160

29

IC161

23





simulation set up

no SSN

no Xtalk

no what-if analysis

tstart : 2000 ns

tstop : 2500 ns

resolution : 2048


















-































7.1.2 Control signal nets

d) Example 4: flash memories control net signal integrity


CS-FLASH

FLASH

IC195

ACTEL FPGA

CPU BOARD

53

54

IC154

2

54

IC155

2

54

IC156

2

54

IC157

2

54

IC158

2

54

IC159

2

54

IC160

2

54

IC161

2

26

Rd-FLASH





simulation set up

no SSN

no Xtalk

no what-if analysis

tstart : 2000 ns

tstop : 2500 ns

resolution : 2048


nets selected : all nets



The differences noted on the pulse width duration between simulation and measurement are due to the

fact that the measurement takes into account the real activity of the CPU board although the simulation

is performed with one pattern selected among several.





CS_flash simulation : IC 154 pin 2

CS_flash measurement : IC 154 pin 2





tr = 11.6 ns

tf = 5.34 ns

























Rd_flash simulation : IC 157 pin 54

Rd_flash measurement : IC 157 pin 54





























e) Example 5: RAM memories control signal integrity


simulation set up

IC163

IC162

RAM

RAM

86

98

CPU BOARD

OE-RAM

IC195

FPGA

6

51 CS-RAM

86

98

87

87

15 RW





no SSN

no Xtalk

no what-if analysis

tstart : 2000 ns

tstop : 2500 ns

resolution : 2048


nets selected : all nets







OE_RAM simulation : IC 163 pin 86

OE_RAM measurement : IC 163 pin 86









RW simulation : IC 163 pin 87

RW measurement : IC 163 pin 87









7.1.3 Data and address signal nets


CPU BOARD

RAM

ex : IC 163

52

46

buffer

ex : IC 181 52 5

IC194

µprocessor

k6

319

116

MUX

ex : IC 174 8

ACTEL

ex : IC 195

23

120 28

FLASH

ex : IC 154

A_F_1

33

26

DATA BUS

ADDRESS BUS

ex : net A_6

ex : net D_0

sh7

B3-0

A_F_3

D_E_0





simulation set up

no SSN

no Xtalk

no what-if analysis

tstart : 2000 ns

tstop : 4000 ns

resolution : 8192


nets selected : clock, control , address and data nets







net A_F1 simulation : IC 195 pin 120





net A_F1 measurement : IC 195 pin 120





net A_F1 simulation : IC 154 pin 28





net A_F1 measurement : IC 154 pin 28





Data bus measurement D_E_0 : IC 154 pin 33

Data bus simulation D_E_0 : IC 154 pin 33









Data bus measurement D_E_0 : IC 174 pin 23

Data bus simulation D_E_0 : IC 174 pin 23









Data bus measurement D_0 : IC 174 pin 8

and IC 194 pin 116

Data bus simulation D_0 : IC 174 pin 8





IC 194 pin 116

IC 174 pin 8





Data bus measurement D_0: IC 174 pin 8

and IC 194 pin 116

Data bus simulation D_0 : IC 194 pin 116





IC 194 pin 116

IC 174 pin 8





Address bus simulation A_F_3: IC 154 pin 26

Address bus measurement A_F_3: IC 154 pin 26









Address bus simulation A_F_3: IC 181 pin 52

Address bus measurement A_F_3: IC 181 pin 52









Address bus simulation A_6: IC 181 pin 5

Address bus measurement A_6: IC 181 pin 5









Address bus simulation A_6: IC 194 pin 319

Address bus measurement A_6: IC 194 pin 319









7.2 Noise on Vcc Plan


The measurement is performed with an active probe either between the two nodes of a decoupling

capacitor or between the Vcc and Ground nodes of a given component.

For measurement with a functional activity on the CPU board, this activity consist in a reading of a

data in RAM memories with a repetitive cycle of 1 µs. It shall be noted that between two reading

cycle, the CPU goes on with its own instruction

simulation set up

no Xtalk

no what-if analysis

tstart : 100 ns

tstop : 5000 ns

resolution : 4096

resolution : 50 ps

nets selected : see table in § 4.2.3.2 page 27











a) Example 6 : noise on 2.5 V

simulation : IC194-19(Vcc2) and IC194-1(Gnd)

config. : only CLK nets

measurement : IC194-19(Vcc2) and IC194-1(Gnd) with reduced

activity on the CPU board









simulation : IC194-19(Vcc2) and IC194-1(Gnd)

config. : all CLK-all ADR (A_xx)-CTR nets

measurement : IC194-19(Vcc2) and IC194-1(Gnd) with a

functional activity on the CPU board









b) Example 7 : noise on 3.3V

simulation : IC194-223(Vcc) and IC194-321(Gnd)


measurement : IC194-223(Vcc) and IC194-321(Gnd) with

reduced activity on the CPU board









simulation : IC194-223(Vcc) and IC194-321(Gnd)


measurement : IC194-223(Vcc) and IC194-321(Gnd) with a










simulation : IC 178-7 (Vcc) and IC178-11 (Gnd)


measurement : IC 178-7 (Vcc) and IC178-11(Gnd) with a

reduced activity on the CPU board









simulation : IC 178-7 (Vcc) and IC178-11(Gnd)


measurement : IC 178-7 (Vcc) and IC178-11(Gnd) with a










c) Example 8 : noise on 5 V

simulation : between the 2 nodes of C68

measurement : between the 2 nodes of C68

WITH ACTIVITY









7.3 Noise on Ground Plan


The measurement is performed with a differential active probe between two different Gnd points

selected on a capacitor gnd node on the board.

The measurement is performed with a functional activity on the CPU board, this activity consist in a

reading of a data in RAM memories with a repetitive cycle of 1 µs. It shall be noted that between

two reading cycles, the CPU goes on with its own instructions

C66-C361

C66-C243





simulation set up

no Xtalk

no what-if analysis

tstart : 100 ns

tstop : 5000 ns

resolution : 4096

resolution : 50 ps

nets selected : see table in § 4.2.3.3 page 30



C63-C311

C63-C66

C63-C64

C313-C157









a) Example 9

simulation : between C361 and C66

-6,0E-02

-4,0E-02

-2,0E-02

0,0E+00

2,0E-02

4,0E-02

6,0E-02

0,0E+00 5,0E-07 1,0E-06 1,5E-06 2,0E-06 2,5E-06 3,0E-06 3,5E-06 4,0E-06 4,5E-06

Time (s)

No

ise

le

ve

l (V

)





measurement : between C361 and C66





b) Example 10


measurement : between C313 and C157 -3,0E-02

-2,0E-02

-1,0E-02

0,0E+00

1,0E-02

2,0E-02

3,0E-02

4,0E-02

0,0E+00 5,0E-07 1,0E-06 1,5E-06 2,0E-06 2,5E-06 3,0E-06 3,5E-06 4,0E-06 4,5E-06

Time (s)

No

ise

le

ve

l (V

)





c) Example 11







d) Example 12


-6,0E-02

-4,0E-02

-2,0E-02

0,0E+00

2,0E-02

4,0E-02

0,0E+00 5,0E-07 1,0E-06 1,5E-06 2,0E-06 2,5E-06 3,0E-06 3,5E-06 4,0E-06 4,5E-06

Time (s)

No

ise

le

ve

l (V

)






-4,0E-02

-2,0E-02

0,0E+00

2,0E-02

4,0E-02

0,0E+00 5,0E-07 1,0E-06 1,5E-06 2,0E-06 2,5E-06 3,0E-06 3,5E-06 4,0E-06 4,5E-06

Time (s)

No

ise

le

ve

l (V

)





e) Example 13



-8,0E-02

-6,0E-02

-4,0E-02

-2,0E-02

0,0E+00

2,0E-02

4,0E-02

6,0E-02

8,0E-02

1,0E-01

0,0E+00 5,0E-07 1,0E-06 1,5E-06 2,0E-06 2,5E-06 3,0E-06 3,5E-06 4,0E-06 4,5E-06

Time (s)

No

ise

le

ve

l (V

)





f) Example 14







-2,5E-01

-2,0E-01

-1,5E-01

-1,0E-01

-5,0E-02

0,0E+00

5,0E-02

1,0E-01

1,5E-01

2,0E-01

2,5E-01

0,0E+00 5,0E-07 1,0E-06 1,5E-06 2,0E-06 2,5E-06 3,0E-06 3,5E-06 4,0E-06 4,5E-06

Time (s)

No

ise l

evel

(V)





8. ANNEXE :

Synthetis of results acquired with a multiboard

system





8.1 Configuration with a CPU board and an IO board interconnected

through a backplane normally routed

The CPU board and the IO board are connected through a backplane board. Datas are exchanged

between the CPU and the IO board through a multiplexed Address/datas numerical bus. These

exchanged are sampled by control signals such as clock signal, request and acknowledge signals.

BOARD3

Backplane

BOARD2

IO

BOARD1

CPU









8.1.1 Signal integrity check

8.1.1.1 Control signal nets


CPU BOARD

IC72

IC195

CLK_L2

98 17 10

RDY_L2

REQ_L2 R573

A3 C2 B2 P11

A3 C2 B2 J72

J102 J92





IC51

83

72

48

R779

A3 C2 B2

CLK_L2

RDY_L2

REQ_L2

A3 C2 B2

Backplane

board

J82

P2

A3

C2

B2

A3

C2

B2









simulation set up

no what-if analysis

tstart (ns) : 100

tstop (ns) : 1000

resolution : 4096


nets selected : clock net : CLK_L2, control nets : RDY_L2, REQ_L2, address and data nets :

SCSB_AD







simulation on CLK_L2 : J72-A3





measurement on CLK_L2 : J72-A3































simulation on RDY_L2 : J72-B2

measurement on RDY_L2 : J72-B2















































































































































8.1.1.2 Address/Data signal nets


CPU BOARD

IC168

SCSB_AD(0)

98 17

Backplane

board

IC171

IC172

P10

J71

J81

P1

SCSB_AD(12) SCSB_AD(35)

8 8 20 21

SCSB_AD(22)

A1 D12 A8 A5

A1 D12 A8 A5

A1 D12 A8 A5

A1 D12 A8 A5

SCSB_AD(0) SCSB_AD(12) SCSB_AD(35) SCSB_AD(22)

8 8 20 21

IO BOARD

A1

D12

A8

A5

A1

A8

A5

D12

J91 J101





simulation set up

no what-if analysis

tstart (ns) : 100

tstop (ns) : 1000

resolution : 4096


nets selected : clock net : CLK_L2, control nets : RDY_L2, REQ_L2, address and data nets :

SCSB_AD









SCSB _AD(3)

SCSB _AD(0)











SCSB _AD(3)

SCSB _AD(0)





















































































































































simulation on SCSB_AD(35) : J71-D12





measurement on SCSB_AD(35) : J71-D12






























































8.2 Configuration with a CPU board and an IO board interconnected

through a backplane willingly degraded.

The configuration is the same than the previous one, the difference is that we’ve willingly degraded the

backplane.

On the backplane willingly degraded :

the clock shield has been suppressed

the request and acknowledge control signals have been routed nearer to the clock signal (as close

as possible and in a parallel straight traces) to cause the maximum of crosstalk noises on these

signals.

the ground plane has been reduced to an area filled net (less than 1 mm in width) so as to

increase the common mode noise induced in the backplane






8.2.1.1 Control signal nets


CPU BOARD

IC72

IC195

CLK_L2

98 17 10

RDY_L2

REQ_L2 R573

A3 C2 B2

A3 C2 B2 P11

J72

J102 J92

A3 A3





IC51

83

72

48

R779

A3 C2 B2

CLK_L2

RDY_L2

REQ_L2

A3 C2 B2

Backplane

board

J82

P2

C2

B2

C2

B2





simulation set up

100% SSN

Xtalk

no what-if analysis

tstart :

tstop :

resolution :









































































































































































































8.2.1.2 Address/Data signal nets


CPU BOARD

IC168

SCSB_AD(0)

98 17

Backplane

board

IC171

IC172

P10

J71

J81

P1

SCSB_AD(12) SCSB_AD(35)

8 8 20 21

SCSB_AD(22)

A1 D12 A8 A5

A1 D12 A8 A5

A1 D12 A8 A5

A1 D12 A8 A5

SCSB_AD(0) SCSB_AD(12) SCSB_AD(35) SCSB_AD(22)

8 8 20 21

IO BOARD

A1

D12

A8

A5

A1

A8

A5

D12

J91 J101





simulation set up

100% SSN

Xtalk

no what-if analysis

tstart :

tstop :

resolution :





































































































































































































































































































































8.3 Noise on the backplane logical ground


The measurement is performed with a differential active probe between two different Gnd points

selected on the logical ground of the backplane.

The BMC has been willingly degraded. The ground plane has been partially replaced by ground net

routed between connectors ground points.

J71

J72

J81

J82

J101

J102

J91

J92





simulation set up

100% SSN

Xtalk

no what-if analysis

tstart :

tstop :

resolution :













simulation : between J102-B8 and J72-B8





measurement : between J102-B8 and J72-B8

-1,2E-02

-7,7E-03

-3,8E-03

0,0E+00

3,8E-03

7,7E-03

1,2E-02

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-1,0E+00

-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

6,0E-01

8,0E-01

1,0E+00

1,2E+00

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-4,0E-01

-3,0E-01

-2,0E-01

-1,0E-01

0,0E+00

1,0E-01

2,0E-01

3,0E-01

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-5,0E-01

-4,0E-01

-3,0E-01

-2,0E-01

-1,0E-01

0,0E+00

1,0E-01

2,0E-01

3,0E-01

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-1,0E+00

-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

6,0E-01

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

6,0E-01

8,0E-01

1,0E+00

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-1,0E+00

-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

6,0E-01

8,0E-01

1,0E+00

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise l

evel

(V)






-1,0E-01

-5,0E-02

0,0E+00

5,0E-02

1,0E-01

1,5E-01

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise l

evel

(V)
















-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-6,0E-01

-5,0E-01

-4,0E-01

-3,0E-01

-2,0E-01

-1,0E-01

0,0E+00

1,0E-01

2,0E-01

3,0E-01

4,0E-01

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-1,0E+00

-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

6,0E-01

8,0E-01

1,0E+00

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)











-8,0E-01

-6,0E-01

-4,0E-01

-2,0E-01

0,0E+00

2,0E-01

4,0E-01

6,0E-01

8,0E-01

1,0E+00

0,0E+00 2,0E-07 4,0E-07 6,0E-07 8,0E-07 1,0E-06 1,2E-06

Time (s)

No

ise

le

ve

l (V

)