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LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
A. Boyer1, Manuel Gonzalez Sentis1,2, Chaimae Ghfiri1,2, Andre Durier2
1CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France2IRT Saint-Exupéry, 118 route de Narbonne, CS 44248, Toulouse, France
Modelling long-term electromagnetic emission of DC-DC converter
1
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Context
Conducted emission
Gradual degradation of components of the SMPS due to aging Impact on the parasitic electromagnetic emission ? Prediction by simulation of the evolution of emission ? Anticipate risk of non-compliance? Select the appropriate component?
Two parts:1. Modeling of the conducted emission of a SMPS for aging study2. Study thermal aging impact on conducted emission, modeling and validation
Switch-Mode Power Supply
Conducted emission
Radiated emission
Aging (temperature, electrical stress, vibration)
2
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
A. Boyer1, Manuel Gonzalez Sentis1,2, Chaimae Ghfiri1,2, Andre Durier2
1CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France2IRT Saint-Exupéry, 118 route de Narbonne, CS 44248, Toulouse, France
Modeling methodology of the conducted emission of a DC-DC converter board
3
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Outline
1. Presentation of the case study2. Modelling approach of the equipment3. SMPS modelling4. EMC test bench modelling5. Common-mode impedance SMPS– reference plane6. Simulation of conducted emission
4
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Presentation of the case study
Buck synchronous converter,built around controller LT3800Input = 12 V, Output = 5 V, 10 A
max, 200 kHz, burst mode.
Simplified electrical diagram
12 V
+
+ To ext. load
LT3800
L
D
Out 5 V
To ext. battery
VBAT
Vss0 V
SW
Vss
Q1
Q2
10 µH
2 x 100 µF
100 µF 2 x 22 µF
12 V input5V reg. output
LT3800 controller
NMOSFET (STB140NF75T4)
Schottky (MBRB1660)
59 mm
55 mmNMOSFET (STB140NF75T4)
ceramictantalum
tantalum
5
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Presentation of the case study
Installation in a typical normative set-up for conducted emission
DC-DC converter board
Cable harness (L=1.2m, h = 50
mm)LISN
12 V
Reference ground plane
Dum
my
load
(4.7
Ω)VBAT
VSS_in
Out
VSS_loadVSS_Ref
I DM
mea
s.
I CMm
eas.
V BAT
LISN
m
eas.
V SS
LISN
m
eas.
ZCM board
6
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Modelling approach of the equipment
Bottom-up approachConstruction of white or grey box model of
componentsExtraction of component models from
measurementsExtraction of PCB model from simulation
₋ Less accurate and more complex extraction than a full black-box approach
₊ Components model appear explicitly component’s aging model can be included₊ EMC prediction prior fabrication of the equipment₊ Influence of design choice can be simulated (e.g. component change, load, placement)
Active devices
PCB
Connectors
Passives
7
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
SMPS modelling – Definition of terminals
VBAT
VSS_in
VSS_Ref SW
Out
VSS_load
Physical port (connectors)Non physical port (common-mode path)
Large Vss plane Large dv/dt
DC-DC converter board model
8
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
SMPS modelling – Passives models
2 ports VNA measurements (Z(f))
Extract equivalent RLC model
e.g. 100 µF Tantalum capacitor (Vishay TR3C107K010)
I(V) and C(V) measurements for Schottky diode SPICE model extraction
9
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Gate command (V(t))
Vss
SMPS modelling – Power MOSFET model
Extracting a model from measurements is a complex task due to non-linear behaviorChoice of model is a compromise between accuracy and model complexityHybrid proposed approach:
Sakurai Newton model (I(V), Rdson)
Junction capacitance (C(V))
Body diode (I(V), C(V))
source
gate
drain
Ross (Z(f))
Package inductance (Z(f))
10
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
SMPS modelling – PCB model
Touchstone file export Black-box model
Small boardMain effect to include is the parasitic inductance along the resonant loop formed by Schottky
diode, MOSFETs and input capacitor
12 V
+
+ To ext. load
LT3800
L
D
Out 5 VTo ext. battery
VBAT
Vss0 V
SW
Vss
Q1
Q2
10 µH
2 x 100 µF
100 µF 2 x 22 µF
Resonant loop
Typical approach:3D electromagnetic
simulator
11
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
EMC test bench modelling
Cable, LISN and dummy load modeling of common/differential-mode propagation is criticalMixed-mode S parameters is a suitable format to understand CM-DM issues :
Port 1
[ ] [ ][ ][ ] 1−=
= TST
SSSS
S SECCCD
DCDDMM
[ ]
−=
1111
21T
conversion
12
DUT
[SSE]
Ref
Port 2
Ref
V1
V2
I1
I2
Single-ended representation
Port Diff+
DUT
[SMM]
VDiff
VCM
IDiff
ICM
Mixed-mode representation
Port Diff-
Port CM+
Port CM-
Example: LISN model – Construction from Mixed-mode Z parameter measurements:
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Common-mode impedance SMPS – reference plane
Impedance Vss board plane – ref. plane: floating rectangular plane capacitve behaviour
SS
hS
CCC riPCM+
+=+=π
εεε 00 7.151.1
hLCM 0µ=22395
=λhRCM
Impedance SW node – ref. plane: complex shape electromagnetic simulation
Port1 (SW)
Port2 (Vss plane)
≈ 3 pF
≈ 0.15 pF
13
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Simulation of conducted emission
Simulation in time and frequency domain (receiver bandwidth taken into account in simu.)Case 1: 4.7 Ω load and floating Vss plane
Ripple amplitude : OKTime-domain profile + 34 MHz oscillation : OK
CE LISN CE currentprobe
Good correlation up to 30 MHz (validity of LISN model)
Resonance at 34 MHz modeledCM current strongly dependent on capacitance with SW node14
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Simulation of conducted emission
Two extra cases in simulation
1 Ω + floating Vss plane 4.7 Ω + shorted Vss plane
15
CM c
urre
nt
on c
able
CE o
n LI
SN
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Conclusion
Satisfying approach to predict the global trend and the maincharacteristics of conducted emission spectrum produced by DC-DCconverter
Black-box modeling approach would certainly provide a betteraccuracy since it is based on measurement results
The effect of change of load, component or equipment mounting onthe EMC test bench can be simulated.
The influence of aging of components should be simulated.
16
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
A. Boyer1, Manuel Gonzalez Sentis1,2, Chaimae Ghfiri1,2, Andre Durier2
1CNRS, LAAS, 7 avenue du colonel Roche, F-31400 Toulouse, France2IRT Saint-Exupéry, 118 route de Narbonne, CS 44248, Toulouse, France
Study of the thermal aging effect on the conducted emission of a synchronous buck converter
17
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Context
Conducted emission
Gradual degradation of components of the SMPS due to aging Impact on the parasitic electromagnetic emission ? Prediction by simulation of the evolution of emission ? Anticipate risk of non-compliance? Select the appropriate component?
Two parts:1. Modeling of the conducted emission of a SMPS for aging study2. Study thermal aging impact on conducted emission, modeling and validation
Switch-Mode Power Supply
Conducted emission
Radiated emission
Aging (temperature, electrical stress, vibration)
18
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Outline
1. Modeling approach of aging impact2. Effect of aging on conducted emission3. Characterization of components after aging4. Passive device model extraction5. Simulation of effect of aging on conducted
emission
19
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Modelling approach of aging impact
Individual accelerated thermal aging of components mounted on the DC-DC converterboard
Accelerated thermal aging of DC-DC converter boards (150°c, 3 weeks max.) I(V), C(V), Z(f) characterization of components during the stress period Identification of most degraded components Extraction of equivalent models before / after stress Comparison between measurement and simulation of evolution of conducted emission
for validation purpose
Name Reference Type ValueCin1 Murata GRM32ER71E226K 25 V X7R ceramic capacitor 22 µFCin2 Vishay TR3C107K010 25 V Tantalum capacitor 100 µFCout Vishay TR3W107K025 10 V Tantalum capacitorC1 Panasonic EEEFP1E470AP 25 V Aluminum capacitor 47 µFLout Vishay IHLP5050FDER100 Shield powder iron inductor 10 µH
L1 Coiltronics HC9-220High temperature powder inductor 22 µH
Lf Murata BLM21PG600SN1D Chip ferrite bead 60 Ω @ 100 MHzD Fairchild MBRB1660 Schottky rectifier 16 A max
Q1, Q2 ST STB140NF75T4 Power NMOSFETRDSon = 6.5 mΩ 120 A
TVS LittelFuse SMDJ11CA Bidirectional TVS diode VBR = +/- 13 V
20
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Effect of aging on conducted emission
Conducted emission measurement before/after aging (150°c - 330h) Measurements done on 5 identical boards same trends.
12 V
+
+ To ext. load
LT3800
Lout
D
Out 5 VTo ext. battery
VBAT
Vss0 V
SW
Vss
Q1
Q2 Cout (x2)
Cin1 Cin2 (x2)
Increase above 3 MHzNo increase
Shield powder iron inductor
Tantalum capa.
Tantalum capa.
Ceramic capa.
At the input side: At the output side:
21
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Characterization of components after aging
Name Type Stress effectCin1 25 V X7R ceramic capacitor NoneCin2 25 V Tantalum capacitor ModerateCout 10 V Tantalum capacitorC1 25 V Aluminum capacitor HighLout Shield powder iron inductor HighL1 High temperature powder inductor NoneLf Chip ferrite bead ModerateD Schottky rectifier ModerateQ1, Q2 Power NMOSFET ModerateTVS Bidirectional TVS diode Moderate
Summary:
22
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Characterization of components after aging
Characterization results
Aluminum capacitor (gradual increase of ESR)
Iron powder inductor (gradual increase of core loss)
Ferrite bead (slight decrease of real part of impedance)
Schottky diode (slight increase of Ron)
TVS diode (slight increase of Ron and VBR)
MOSFET (sligth increase of VTH, Ron not affected)
23
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Passive device model extraction
Typical capacitor model
Thermal stress↓
Co↓ and ESR↑
ESR model (parallel R-C cells)
Impact of aging on capacitors (Aluminum and tantalum)
Extraction of capacitor models after each stress period (optimization of C0 andRC cells)
24
ESR
ESL
C0
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Passive device model extraction
Thermal overstress↓
Rp↓ and Cp↑
Impact of aging on iron powder inductor
25
RDC
L0
CP
RP
Typical inductor model
Extraction of inductor models after each stressperiod (optimization of L0 and RP)
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Simulation of effect of aging on conducted emission
Initial configuration (tantalum capacitor at input/output and iron powder inductor)Measurement
Correct simulation of the increase of conducted emission at the output side (filtering inductance) and the invariability of the conducted emission at the input side (robustness of tantalum capacitor)
Simulation
Inpu
t sid
eO
utpu
t sid
e
26
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Simulation of effect of aging on conducted emission
Simulation of extra cases:1. Only aluminum capacitors mounted + iron powder inductor
important rise of the input and output CE up to 20 MHz due to weak robustness of aluminium capacitors.
Role of the degradation of iron powder inductor above 20 MHz
Input side Output side
27
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Simulation of effect of aging on conducted emission
Simulation of extra cases:2. Only tantalum capacitors mounted + high temperature inductor
Small increase (+ 2 dB) around the fundamental frequency due to the slight increase of the ESR of tantalum capacitors
No increase of the conducted emission at the output side due to the excellent robustness of the high temperature inductor
Input side Output side
28
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Conclusion
High temperature stress affects conducted emission produced bySMPS (in buck configuration in this study, but simulations confirm that thesame effects arise in other configurations)Role of the degradation of passive devices (especially electrolytic
capacitors and iron powder inductors)Simulation of the long-term evolution of conducted emission is feasible
if the evolution of the impedance vs. aging condition is performed
Perspectives: Accelerated-aging test set-up to cover all stressconditions (design of experiments) and reliability calculation tool toextrapolate emission level drift in other stress conditions (e.g.MSTORM model [1]).
[1]: J. B. Bernstein, E. Bender and A. Bensoussan: “Reliability Prediction with MTOL”. IEEE Transactions on Device and Materials Reliability (2016)
29
LAAS-CNRS/ Laboratoire d’analyse et d’architecture des systèmes du CNRS
Laboratoire conventionnéavec l’Université Fédérale
de Toulouse Midi-Pyrénées
Thank you for your attention
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