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libraryIEEE;useIEEE.std_logic_arith.all;useIEEE.std_logic_1164.ALL;

ENTITYa7sISPORT(

p :INbit_vector(0to6);

s1,s2,s3,s4,s5,s6,s7:OUTbit);

ENDa7s;

ARCHITECTUREarchiOFa7sISsignalseg:bit_vector(6DOWNTO0);BEGIN

PROCESS(p)BEGINCASEpISWHEN"0000000"=>segsegsegsegsegsegsegsegsegsegsegsegsegsegsegsegseg

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ENDarchi;