Cache Op Tim Ization Techniques
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CPU
L1 Data Cache L1 Inst Cache
L2 Cache
Registers
L3Cache
MainMemory
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loop
interchange
stride8 access stride1 access
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1
2
3
4
i
1
2
3
4
i
4321j
4321j
loop
blocking
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x
i
j
x
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M M
NN
K
K
Matrix C Matrix A
Matrix B
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