Ecole micro-lectronique, La londe-les-maures, 14 oct 2009 Pixel
Hybride 3-D en techno 0.13m pour SLHC/ATLAS P. Pangaud S. Godiot a,
M. Barbero b, B. Chantepie a, J.C. Clmens a, R. Fei a, J. Fleury c,
D. Fougeron a, M. Garcia-Sciveres c, T. Hemperek b, M. Karagounis
b, H. Krueger b, A. Mekkaoui c, P. Pangaud a, A. Rozanov a, N.
Wermes b a Centre de Physique des Particules de Marseille, France b
University of Bonn, Germany c Lawrence Berkeley National
Laboratory, California, USA Slide 2 Ecole micro-lectronique, La
londe-les-maures, 14 oct 2009 P.Pangaud Outline Pixel pour
Atlas/LHC Projet SLHC Version 3D MPW TERRAZON/CHARTERED Slide 3
Ecole micro-lectronique, La londe-les-maures, 14 oct 2009 P.Pangaud
Pixels pour upgrade de Atlas/LHC CF=17fF CC/CF2=5.8 Config word=1
2b 4 bits 5 bits Constraints Noise under 100 e - Threshold around
1000 e - Dispersion threshold 200 e - Slide 4 Ecole
micro-lectronique, La londe-les-maures, 14 oct 2009 P.Pangaud
FE-I4/FE-TC4 : Analog Preamplifier Leakage Comp. Transistor Local
Feedback tuning 4b Feedback structure Injection switches and caps
Core Preamp Slide 5 Ecole micro-lectronique, La londe-les-maures,
14 oct 2009 P.Pangaud Hybrid Pixels detector for HEP (Atlas/LHC
example) 50 m FE-I3 CMOS technology : 250 nm 400 m 250 m FE-I4 CMOS
technology : 130 nm Done : ATLAS/LHC (2008/2009) Under Design
ATLAS/LHC upgrade project (2014) And silicon sensor with the same
pixel dimension Slide 6 Ecole micro-lectronique, La
londe-les-maures, 14 oct 2009 P.Pangaud 3-D Hybrid Pixels detector
(Atlas/SLHC example) FE-I3 CMOS technology : 250 nm 400 m 250 m
FE-I4 CMOS technology : 130 nm 50 m Done : ATLAS/LHC 2008/2009
Under Design ATLAS/LHC upgrade project (2014) 50 m 125 m Drastic
pixel dimension reduction (cost effective compared to smallest
technologies ?) Why not ?? ATLAS/SLHC (10 years after LHC..) 50 m
100 m New mechanical possibilities Dream,dream,dream ??? ATLAS/SLHC
Slide 7 Ecole micro-lectronique, La londe-les-maures, 14 oct 2009
P.Pangaud Pixel -> 3-D CF=17fF CC/CF2=5.8 Config word=1 2b 4
bits 5 bits FE-TC4-EA : 2 possible ways for discriminator output
read-out: With the simple read-out part existing yet into the pixel
With the tier 2 (via the Bond Interface) FE-TC4-DS : dedicated for
parasitic coupling studies between the 2 tiers. FE-TC4-DC :
Read-out chip similar to what is foreseen for FE-I4 Slide 8 Ecole
micro-lectronique, La londe-les-maures, 14 oct 2009 P.Pangaud FE-I4
to FE-TC4 FEI4 : IBM 0.13 1P8M LV FEI4 : CHARTERED 0.13 1P5M LP
Bond Interface 5m step TSV 1.5 diameter Slide 9 Ecole
micro-lectronique, La londe-les-maures, 14 oct 2009 P.Pangaud 2d
Tiers -> Simple : Counter + parasitic coupling studies ->
Complex : Read-out chip similar to what is foreseen for FE-I4 M5 M4
M3 M2 M1 M6 SuperContact M1 M2 M3 M4 M5 M6 SuperContact Bond
Interface Tier 2 Tier 1 (thinned wafer) Back Side Metal sensor
Slide 10 Ecole micro-lectronique, La londe-les-maures, 14 oct 2009
P.Pangaud Fermilab 3-D Multi-Project Run Fermilab has planned a
dedicated 3-D multi project run using Tezzaron for HEP during 2009
There are 2 layers of electronics fabricated in the Chartered 0.13
um process, using only one set of masks. (Useful reticule size 15.5
x 26 mm) The wafers are bonded face to face. ATLAS/SLHC Sub-part
Slide 11 Ecole micro-lectronique, La londe-les-maures, 14 oct 2009
P.Pangaud Fermilab 3-D Multi-Project Run The Atlas/SLHC prototype
with 2 tiers FETC4-AE SEU-3D FETC4-DSDC SEU-3D TSV Daisy Chain + BI
TSV vs Transistors + capacitors TSV vs Transistors + capacitors
Mechanical stress DFF + Tr + Cap Mechanical stress DFF + Tr + Cap
SENSORSENSOR Slide 12 Ecole micro-lectronique, La londe-les-maures,
14 oct 2009 P.Pangaud FEC4 -> First results of first chip in
Chartered 0.13LP 1P8M Due to schedule no optimization of
transistors has been done Main results are equivalent to IBM ones.
Threshold min around 1100 e- Un-tuned threshold dispersion 200 e-
Noise lower than 80 e- Problem discovered after 160 MRad on latches
( output tends to be blocked in "1" state) Difficult to work with
the circuit by after Problem reproduced in simulation "corners" (SF
and FS case) but Analog is still working even with increased of
noise : 250 e- (threshold dispersion is meaningless)
