Analog Readout Circuit for Zero Leakage Planar-Hall-Effect-Magnetic-Random-Access-Memory

Anatoli Mordakhay, Student Mebmer, IEEE, Alexander Fish, Member, IEEE Bar-Ilan University, Ramat-Gan, Israel email: anatoli.mordakhay@biu.ac.il

Abstract— An analog readout circuit for use in conjunction with the Planar-Hall-Effect Magnetic-Random-Access-Memory is presented. The non-volatile nature of this type of memory allows zero leakage during memory retention, allowing significant power saving. The circuit employs a novel technique for readout operation of memory bit-cells. The circuit uses chopping and switched-capacitor techniques for amplification of the low input signal as well as elimination of DC-offset and low-frequency noise. The binary nature of the data allows an area efficient implementation at the cost of linearity, which is less significant for memory readout applications. The proposed circuit was implemented in the TowerJazz 180nm CMOS process at a supply voltage of 1.8V, and can reliably sense input signals with amplitude of as low as 1mV.

I. INTRODUCTION Modern integrated circuits (ICs) impose larger memory

performance requirements than ever before. High-speed, low-voltage, low-power consumption, non-volatility, and high-density are just a sample of this long list of demands. This ever growing list of demands pushes memory technology further, with the continuous improvement of existing memory types, as well as design of completely new memory structures. Out of all emerging memory technologies, Magnetic-Random-Access-Memory (MRAM) is often considered a promising memory technology due to its non-volatility, high-density, high-speed, and zero-standby power [1].

Magnetic-Tunnel-Junction (MTJ) [2] is, without a doubt, the most established form of MRAM technology to date. This type of memory has been in development for years. However, this isn’t the only memory technology to take advantage of the magnetic properties of materials. One such type of magnetic memory technology is the Planar-Hall-Effect (PHE) MRAM [3-4]. This type of memory is based on the PHE in magnetic films, and its single-layer structure makes it simpler to manufacture when compared with the MTJ structure.

The PHE-MRAM bit-cell is incompatible with any of the available memory readout circuits used for other memory types, and a different readout circuit must be designed for it. This paper presents, for the first time, a readout circuit intended specifically for use with PHE-MRAM arrays. The proposed circuit combines techniques used in precision sensing applications, such as chopping [5-6]; but foregoes the conventional feedback network and output filter stage used in these circuits. Instead, a low-gain differential amplifier and a switched-capacitor (SC) summing structure are included. These modifications can achieve significant area reduction at

the cost of reduced linearity; however, the latter is of little significance for the intended application.

The rest of this paper is organized as follows: Section II presents the basic structure of the PHE-MRAM and discusses the readout circuit specifications as dictated by the signal coming out of the memory. Section III presents the proposed readout circuit topology as well as the actual transistor level implementation. Section IV presents simulations results for the proposed circuit. The paper is concluded in section V.

II. PHE-MRAM STRUCTURE AND REQUIREMENTS The basic memory structure of the PHE-MRAM is shown

in Fig. 1. The memory is constructed out of a single layer of magnetic material, as was previously presented in [3-4]. The readout operation of the memory is initiated by conducting a current between points A and B of the structure. Then, the output signal is read differentially between points C and D. Depending on the magnetization (M) the signal will be either positive or negative in sign. Therefore, the binary data is stored in the sign of the output signal rather than the amplitude as in single-ended readout memories.

Figure 1: PHE-MRAM Structure

The amplitude of the differential output signal depends on

the angle of the magnetization, the magnitude of the current, and the dimensions of the structure. Recent measurement results show the gain VCD/IAB to be in the order of 0.2-0.3Ω. While it is expected this value will be larger in future generations of this memory technology, it will still impose very strict noise and offset requirements upon the readout circuit.

With such low gain figures, a very large current must flow in the AB path for the output signal to be large enough for use with normal readout circuits. This, in turn, will increase power consumption, and will require larger devices as well as very wide wires to reduce IR-drop and Electromigration effects. It is easily seen that this limitation calls for the use of a very low-noise and low-offset readout circuit to allow detection of

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very small signals, keeping the current in the AB path to a minimum. An acceptable current for the readout application can be up to 10mA at most, which is significantly higher compared to other memory technologies, but acceptable in applications where the memory isn’t accessed continuously. Such applications include low power RFID tags, sensor nodes with low activity factors, and many others. With this 10mA value of current, the differential output signal will be limited to 2-3mV at most, and therefore, the total offset and noise of the readout circuit must remain below this value.

III. READOUT CIRCUIT DESIGN Very low-noise and low-offset amplification, as presented

in the previous section, are requirements rarely seen in the design of memory readout circuits, and are normally encountered in readout circuits for sensor applications [7-8]. In these applications it is common to see very large transistor dimensions for reduced offset and noise, as well as additional circuit techniques such as auto-zeroing and chopper amplifiers. These circuit solutions are well suited for sensor applications, where a very limited number of sensors are incorporated with the IC, and the area allocated to each readout circuit can be made sufficiently large. However, for memory arrays, a large number of such circuits must be integrated on the same chip as the memory core, significantly limiting the area available for the readout circuits. Therefore, a readout circuit must be designed to have both low-noise and low-offset, as well as be small in size.

Figure 2: Readout Circuit Structure

A. Proposed Readout Circuit Topology The proposed readout circuit is presented in Fig. 2. A

chopper has been selected for its very low-offset and low frequency noise. The circuit is completely differential and symmetrical all the way to the comparator at the end; this must be maintained in the layout as well, or coupling from other parts of the IC into the readout circuit may corrupt the data. The differential input signal from points C and D of the PHE-MRAM bitcell is fed into the amplifier through a set of commutating switches as in all chopper amplifiers. This signal is then amplified by the low-gain, differential-input-differential-output amplifier, which is operated with no negative feedback loop around it. The output of the amplifier is fed into a SC summing structure that serves as the filter and adds additional gain. Finally the two signals are compared, and the output signal is taken at the output of the comparator.

As with all sampling circuits, the SC structure will fold out of band noise into the frequency band of interest. Therefore the signal must be low-pass-filtered before sampling. In the proposed topology, this filtering action is achieved by the

combination of the amplifier output resistance and the load capacitance presented by the SC structure.

B. Amplifier Structure In most applications where chopper amplifiers are used,

analog signals are of interest, and the linearity of the amplifier is of great importance. This, in turn, calls for the use of a high-gain amplifier inside a negative feedback loop for precise setting of gain. However, in this memory readout application, the amplitude of the signal is of no importance, as the data is stored in the sign of the differential signal. This allows the gain to vary significantly without it affecting the operation of the circuit, as long as the gain remains sufficiently large. Obviously, since no feedback is used, the open loop gain must be relatively low when compared with Operation-Transconductance-Amplifiers (OTA) or else any small offset or signal at the input will cause the amplifier to saturate. The structure of the proposed amplifier is shown in Fig. 3.

Figure 3: Differential-Amplifier Structure

The input differential-pair is PMOS devices (M0-M1) for

their lower noise, and for the usability down to lower input common-mode (CM) voltage. The input pair is loaded by diode connected NMOS devices (M2-M3), comprising a current mirror with the adjacent NMOS devices (M4-M5). These currents are then converted into the output voltages by flowing through diode connected PMOS devices (M6-M7). The inclusion of current mirrors M2-M4 and M3-M5 is required for sufficient voltage gain. A gain of gm0/gm6 is attained instead of the lower value of gm0/gm2 when the output signal is taken over the diode connected NMOS devices and not PMOS devices. This difference in gain is attributed to increased gm of NMOS devices due to their higher mobility. Transistors M8-M9 are used to supply a small current, which in turn decreases the quiescent current in M6-M7, decreasing their gm and increasing the gain of the amplifier.

C. Switched-Capacitor Summation Normally, the amplifier will be followed by another set of

switches and an active filter to remove high frequency content from the amplified version of the input signal. This active filter will have an amplifier with passive devices in the feedback loop to set the transfer function precisely. As with the amplifier, the reduced requirement for linearity allows the filter design to be significantly simplified. Fig. 4 shows the structure of the SC summing circuit used to strip the output signal from the offset and low frequency noise introduced by the amplifier.

This entire circuit is duplicated once more to obtain a fully differential signal, and is operated with the same control

phases as the commutating switches at the input of the entire readout circuit. “In1” is connected to “Out+” of the differential amplifier; “In2” is connected to “Out-“ of the differential amplifier; and “OutSC” is connected to the positive input of the following comparator (shown in bold). For the second copy of this circuit, signals “Out+” and “Out-“ from the amplifier are interchanged and “OutSC” is connected to the negative input of the comparator. This scheme adds “Out+” of the first phase with “Out-“ of the second phase in one SC circuit, and “Out-“ of the first phase with “Out+” of the second phase in the second:

From previous stages we know that:

Combining all of these we can find that the differential output voltage is given by:

Therefore, the described connection both removes the offset and low-frequency noise from the differential output signal as required, and also adds an additional 6 dB of gain by summing the amplified signals from both phases.

Figure 4: SC Summing Structure

The expected voltage levels at each node are such that

single-transistor switches can be used without the need for an additional inverse-polarity device in parallel, as normally used for analog switches. The reduced linearity requirement allows the use of an N-Well accumulation capacitor. This considerably reduces the area for the same capacitance value but increases the dynamic power, due to the higher parasitic capacitance of this capacitor type.

D. Comparator The comparator is presented in Fig. 5. It is a latch, with the access transistors missing as they are incorporated into the SC circuit presented in the previous sub-section. Transistors M0-M1 are used to isolate the supply voltages to allow the outputs from the SC to be loaded into the comparator nodes, and transistors M2-M5 compose a pair of cross-coupled inverters. Transistors M6-M7 are reset transistors and are absolutely

required for reliable operation of this circuit. The operation of the comparator is very straightforward with a reset phase at which both internal nodes are connected to each other. The next phase is connection of the comparator inputs to the SC circuits to charge them with the amplified differential signal. Finally, connecting both supply rails enables the positive feedback of the cross-coupled inverters to pull the circuit to one of its stable points according to the initial condition.

The reset of the comparator in this application is necessary to minimize hysteresis effects. Without a reset before each comparison, the internal nodes of the comparator will remain at the same voltages as they were after the previous comparison - VDD or GND. Each node has some capacitance associated with it, and when it is connected to the output of the SC stage, charge sharing will occur. This charge sharing will degrade the signal from the previous stages, and in extreme cases may cause a readout error.

Figure 5: Comparator Structure

IV. SIMULATIONS RESULTS The proposed topology was designed and simulated using

Tower-Jazz 180nm process at the nominal 1.8V supply voltage. Fig. 6 shows the layout of the circuit.

Figure 6: Layout of all circuit stages

Input and output waveforms of the amplifier are presented

in Fig. 7. An input signal of ‘0’ followed by a ‘1’ with differential amplitudes of 2mV are fed into the chopper at the input, and amplified with a 30 dB gain. An input offset of 10mV has been introduced to present the cancelation of the offset at the differential output following the SC stage. The simulation data clearly demonstrates the ability of the proposed circuit to reconstruct the data under these conditions. The amplified signal at the output of the amplifier shows the charging time of the load capacitors, and the amplifier must

have sufficient current drive capability and bandwidth to charge the capacitors within this available time window.

Figure 7: Amplifier Input and Output signals

The amplified signal is then connected to the SC for

summation; the waveforms of this stage are shown in Fig. 8. The “Sample” signal is asserted during the first phase, charging the capacitors to the output voltages of the amplifier, followed by the assertion of the “Evaluate” and “EvaluateB” signals during the second phase. “EvaluateB” is only allowed to be low for the first half of that phase. This leaves sufficient time during the second half of this phase, for the comparator to evaluate the data without charging/discharging the high capacitance of the SC circuit, reducing power consumption and evaluation time.

Figure 8: SC Control and Data signals

Figure 9: Comparator Control and Data signals

Finally, the operation of the comparator is presented in Fig. 9. The comparator is reset during the first phase of operation before each comparison. The reset is completed in a very short time; therefore it can be made just before the insertion of the new signals, keeping the output data of the previous cycle available for read up to this moment. In the second phase, the signals are initially transferred from the previous stage into the comparator as can be seen once the

reset signal is pulled back up. Subsequently, the comparator is connected to the supply rails, enabling the positive feedback of the cross-coupled inverters, and pulling the data nodes to opposite supply rails as dictated by the input signals.

Table 1 summarizes the main characteristics of the circuit.

Technology TowerJazz 180nm

Supply voltage 1.8V

Minimum detectable signal 1mV

Total Power 33μW

Readout time 0.1μS

Area 38μM*24μM

Table 1: Main characteristics of the proposed circuit

V. CONCLUSIONS This paper presents an analog readout circuit tailored for

operation with the PHE-MRAM bitcell. The main design goals of the readout circuit are low-noise and offset for reliable readout with minimal error probability, as well as low power and area consumption. These goals are achieved by adapting circuit techniques normally reserved for sensors readout applications, and making some modifications, which are acceptable considering the nature of the input signals.

Future work will include fabrication of the proposed readout circuit and the integration of the PHE-MRAM using post-processing techniques for verification of the performance of the entire system.

ACKNOWLEDGMENTS The authors would like to thank Prof. L. Klein for his

constructive comments and suggestions.

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