Cours Circuits Intégrés Analogiques - 2008/2009 - 29/04

Cours Circuits Intégrés Analogiques - 2008/2009 -Chapitre II

29/04/2010

1

Polytech’MontpellierERII 4

Design of Analog IC’s

Chapitre IVAdvanced Analog Design Techniques

Pascal Nouet – March 2010

[email protected]

Outline

• Analog IC Design Flow

• Advanced specifications

• Advanced design techniques

2

SpecificationsSpecificationsChoice of the architectureChoice of the architecture

Initial sizing (1st order models)


DC simulationsDC simulationsAC small-signal

simulationsAC small-signal

simulationsMC Simulations MC Simulations

Application-Specific

Simulations (DC, AC, MC)



LayoutLayoutPost-layout simulationsPost-layout simulations

SpecificationsChoice of the architecture


DC simulationsAC small-signal

simulationsMC Simulations



LayoutPost-layout simulations

Just to be sure !!!next step cost $

(10 -100k$) and time (few weeks to few months)

Analog IC Design Flow3

gain, bandwidth, noise, slew-rate, stability, CMRR,

PSRR, input and output dynamic ranges, output resistance,

output current, …

number of stages, output stage,

folded cascode, differential output, …

operating point, saturations, input and output ranges,

gain, output resistance and

current, …

stability, gain, bandwidth, CMRR,

PSRR, capacitive load effects, …

Verify cell specifications vstechnology spreadings

(variability) and mismatchesTemperature and Power

Supplies

Verify system-level specifications

From the designer point of view: THE fabrication

(analog layout is more expert than digital layout)

Analog IC Design Flow4

SpecificationsSpecificationsChoice of the architectureChoice of the architecture



DC simulationsDC simulationsAC small-signal

simulationsAC small-signal

simulationsMC Simulations MC Simulations





LayoutLayoutPost-layout simulationsPost-layout simulations

Outline


• Advanced specifications– Offset considerations

– Common Mode Rejection Ratio

– Design for low mismatches

– Noise fundamentals

– Characterization


5Offset considerations

• Definition: “input offset” of a differential amplifier is the differential input voltage that leads to a zero output voltage

6

Symmetrical power supplies !!!


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2

Offset considerations

• Impact of offset on a simple design: high for low-input levels

• The gain is 60 instead of 100

7

mViRvvk

vvi inFosout

osinin 596.

1−=−=→

Ω−=


• Offset is a random phenomenon due to:– Technology spreading low “frequency” variations

(die to die ; wafer to wafer ; run to run)

– Mismatches high “frequency” variations (device to device)

– Variability hot topic covering both previous origins

• affecting technology parameters and dimensions

• generally following a Gaussian distribution.

• Propagation to circuit behavior– Example: incertitude on saturation current

– µCox, W/L and Vt are affected

8

( )22 tgs

oxdsat VV

L

WµCI −=


• Gaussian distribution basics– For a large number of identical devices the

distribution of actual Vt (µCox, W/L) follows a Gaussian distribution

– 0.5% of the values are more than ±3σ away from the average value

– 6σ designs are then the standard in industry 99.5% of yield in absence of defects

– Run to run σ (technology spreading) is much higher than device to device σ (mismatches) MC simulations

9

).(4 µmmVNtA

WL

A

BoxV

VV

t

t

t

∝

=σ


• Standard deviations are related to design !!!– Set of equations can be

found in the literature

– Vt spreading increases with the substrate doping and the oxide thickness

– Vt spreading decreases with the area of the transistor

– PMOS fabricated in a N-well exhibits more Vt

spreading (ND>>NA)

– Overall, Vt spreading reduces with modern technologies (seems to saturate at around 3mV.µm)

10


• µCox mismatches– Similar expressions than for Vt

• W/L mismatches

• Example: 100µm/1µm NMOS in a 0,6 µm tech.

– 50% more for a PMOS

– 10 times less for MOST on the same die (mismatches)

11

µm0056,0A

WL

A

µC

ox

oxox

µC

µC

ox

µC

≈

=σ

%2,0600

2,1 ==mV

mV

Vt

Vtσ

%056,000056,0 ==ox

µC

µCox

σ

µmALW

ALW

LW

LWLW

02,0

11

/

/

22//

≈

+=σ

%2// =LWLWσ


• Random offset in a current mirror

• Design tips Large area and Veff, long

• W=100µm ; L=1µm ; Veff=0,1V

• W=10µm ; L=10µm ; Veff=1V

12

( )22 tgs

oxdsatS VV

L

WµCII −==

Vs

Iin IS

T1 T2

LWµCVVILW

ox

µC

tgs

V

S

I oxtS

/

.2/σσσσ

++−

=

%24,0 ppm56 %2,0

%024,0 ppm56 %028,0


29/04/2010

3

We’ve already studied…

• Analog design flow– A design must fit specifications in the typical case

– A design must also fit specifications for all possible combinations of: process (variability in process parameters and dimensions), temperature and power supply 6σ designs

• Advanced specifications and variability– Uncertainties translate in a Idsat standard deviation

– Random offset in a simple current mirror…

• Large transistors and large Veff

13

.../

.2/ +++

−=

LWµCVVILW

ox

µC

tgs

V

dsat

I oxtdsatσσσσ

Some variability parameters (wafer to wafer)

µmmVA

µmmVAWL

A

t

t

t

t

V

V

VV

.8

.12

≅

≅

=σ

µmA

WL

A

µC

ox

oxox

µC

µC

ox

µC

0056,0≈

=σ

µmALW

ALW

LW

LWLW

02,0

11

/

/

22//

≈

+=σ


• Random offset in a differential pair with resistive load and symmetrical supply voltages

• Spreading in load resistance

• Other spreading

14

eff

BLLm

os

od

V

IRRg

v

v ==

22eff

L

Los

BLod

V

R

Rv

IRv

∆=⇒∆=

LW

LW

µC

µC

V

V

I

I

ox

ox

eff

t

dsat

dsat

/

/.2 ∆+∆+∆=∆

∆+∆+∆+∆=⇒LW

LW

µC

µC

R

RVVv

ox

ox

L

Lefftos /

/

22

.

eff

dsat

dsatos

dsatLod

V

I

Iv

IRv

∆=⇒

∆=


• But offset can be also systematic – due to the chosen architecture, the bias point, a

wrong layout (systematic mismatch)…

– Must be fixed by designer !!!

• Examples– Related to design (layout)

– Related to usage

• If Vds2>Vds1 (Vt+Veff1)

15

2outSmin2out2outS1eff3eff iRgiiiRVV −=⇒−=

( )1ds2dsoutin1out VVgii −+=

Outline








16

Common Mode Rejection Ratio, CMRR

• Definition: CMRR characterizes the ability of a differential amplifier to reject the common mode

17

MC

d

A

ACMRR=

-

+Vd

2d

MC

VVV +=+

2d

MC

VVV −=−

MCMCdds VAVAV ⋅+⋅=

=−=

MC

ddBMCdBddB A

AAACMRR log20,,


• Random CMRR in a differential pair

• Impact of spreading in RL

– vinc vinc/RB in the current source output resistance

18

∞≈⇒==

===

=

=

CMRRv

vA

V

IRRg

v

vA

id

inc

vinc

odmc

eff

BLLm

vid

odd

00

0

LL

Bm

B

L

vinc

odmc

B

incLod RR

RgCMRR

R

R

v

vA

R

vRv

id∆

=⇒∆==⇒∆=⇒

=

2

220


29/04/2010

4


• Without RL spreading, vinc/(2.RB)in each load resistance

• Impact of spreading in MOST

19

LW

LW

µC

µC

V

V.2

R

RRg2

A

RgCMRR

LW

LW

µC

µC

V

V.2

R2

R

v

vA

I

I

R2

vR)R(IRv

ox

ox

eff

t

L

L

Bm

mc

Lm

ox

ox

eff

t

B

L

inc

odmc

dsat

dsat

B

incLLLod

∆+∆+∆+∆==⇒

∆+∆

+∆

==⇒

∆=∆=

Random CMRR and offset trade-off

• Design of low offset and high CMRR differential pair

• The lower the offset, the higher the CMRR

1. Optimize for low offset– Low Veff (0,1V), large transistors, matched resistors reduce Vt spreading and current mismatch

2. Optimize for large CMRR High gm(IB) & RB

20

LW

LW

µC

µC

V

V

R

RRg

CMRR

ox

ox

eff

t

L

L

Bm

∆+∆+∆+∆=.2

2

∆+∆+∆+∆=LW

LW

µC

µC

R

RVVv

ox

ox

L

Lefftos 2

BBBeffmos RIRVgCMRRv ==⋅

Systematic CMRR

• Current source output resistance: RB

• Common Mode Vinc change bias current Vinc/RB

• Vinc/RB equally shares between T1 and T2

• Small-signal analysis to calculate induced output voltage

21

V+ V-

Ibias

T1 T2

Id1 Id2

Vdd

T3 T4

Vout

Id4

B1ds3m2m Rrgg2CMRR=

Outline








22

Design for low mismatches

1. Equal nature

2. Same temperature

3. Increase size

4. Minimum distance

5. Same orientation

6. Same area/perimeter ratio

7. Round shape

8. Centroïde layout

9. End dummies

10. Bipolar always better !

23Design for low mismatches

1. Equal nature

2. Same temperature

3. Increase size

4. Minimum distance

5. Same orientation

6. Same area/perimeter ratio

7. Round shape

8. Centroïde layout

9. End dummies

10. Bipolar always better !

24

Much

Vs

Iin IS

T1 T2

Much

Vs

Iin IS

T1 T2

2 : 1 : 2Vs

Iin IS

T1 T2

2 : 1 : 2

2 : 1 : 2


29/04/2010

5

Outline








25Noise considerations

• Noise is any unwanted signal that interferes with a desired signal. – It can be deterministic or random.

– It can be inherent to the circuit itself or coming from interferences with the outside world.

• Interference noise is caused by an identifiable external source. It can be deterministic or random.– e.g.: 50Hz hum in a loudspeaker, cellular phone interfering with a TV set, …

– It can usually be eliminated by proper methods of grounding, shielding, etc (electromagnetic compatibility, EMC)

• Inherent noise is generated by the circuit itself. It is always random.– e.g.: resistance and transistors are noisy

– Different shape of random noises are thermal, shot and flicker

– It can not be eliminated (inherent) but its effects can be reduced by changing the circuit structure or the power consumption.

26

• Uncorrelated with any of the system inputs

• Equivalent input noise

• Time-domain analysis– Null mean value

– Can be represented by a voltage (thevenin source) or a current (norton source)

– Noise is defined by a root mean square (rms) value

– Signal-to-noise ratio (SNR)

Random noise basics27

∫=T

nrmsn dttVT

tV0

2)( ).(

1)(

=

=

=

)(

)(

2)(

2)( log20log10log10

rmsn

rmss

rmsn

rmss

n

s

V

V

V

V

P

PSNR

• Noise combination– Different noise sources combine as

voltages in series and current in parallel

– Assuming uncorrelated noise sources

Random noise basics28

[ ]

∫

∫

++=

+=

T

nnrmsnrmsnrmsno

T

nnrmsno

dttVtVT

VVV

dttVtVT

V

0 212

)(22

)(12

)(

0

221

2)(

).().(2

.)()(1

2)(2

2)(1

2)( rmsnrmsnrmsno VVV +=

Random noise basics

• Frequency-domain analysis– Noise spectral density

– Noise is considered only in the bandwidth of the system filtered out elsewhere

– Noise rms value @ 100Hz for a 90Hz bandwidth?A 0.1 Hz bandwidth?

29Random noise basics

• Noise Spectral Density (NSD) main shapes– White noise as of a resistor constant spectral density (e.g. 3.2µV/√Hz)

– Flicker noise (or 1/f noise or pink noise) large contribution in low frequencies

• actually inversely proportional to √f

• 1/f noise falls off at -10dB/decade two frequency decades means noise magnitude divided by ten

– Typical NSD of a system as of a transistor-based system

30

[ ]101.0

22)(

10

1.0

22

)(

)ln(10

.10

fµVV

dff

µVV

rmsn

rmsn

=

= ∫


29/04/2010

6

Inherent noise models31

k = 1.38× 10−23 J.K-1

32

1/f noise tangent principle !!!

Noise considerations

• Basic considerations regarding noise in feedback systems

– Vn1 represents the input noise in vi, the equivalent input noise of A1 and the output noise of b,

– Vni2 represents the equivalent input noise of A2

35Outline








36


29/04/2010

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Characterization

• Makes use of MC simulations

• Define a DOE

• Example : error in a current mirror– Set 1 : 100 runs, T1=T2

• Studied influences : Veff (Iin), WL, W/L, L

• Initial design : Veff=0,2V ; W/L=10 ; L=1µm ; Vs =2V

• MC process :

• MC process & mismatch :

37

Vs

Iin IS

T1 T2

µA28VL

W

2

CµII 2

effoxn

1dsatin ===

( ) ( ) ?Imean?I 2dsat2dsat ==σ ;


Characterization

• Effect of Veff .1V < Veff < 2V

– Iin = [10µA ; 50µA ; 100µA ; 200µA ; 500µA ; 1mA ; 2mA]

– MC Process & mismatch :

• Effect of W/L : keep WL and Veff constant

– W/L = [.1 ; .2 ; .5 ; 1 ; 2 ; 5 ; 10 ]

38

Vs

Iin IS

T1 T2mA8.2VL

W

2

CµIµA7V

L

W

2

CµI 2

effoxn

in2

effoxn

in <=>= ;


L

W

10

µA28µm10.

W

Lµm10.

L

WWµm10WL 222 ===⇒= inI ; L ;

Characterization

• Effect of L : keep WL and Veff

constant

– L = [1 ; 2 ; 5 ; 10 ; 20]

• Effect of WL : keep W/L and Veff constant

– WL (µm2) = [7 ; 20 ; 50 ; 100 ; 200 ; 500 ; 1000 ; 2000]

39

Vs

Iin IS

T1 T2


µA2810

WLLWL.10W10L/W ===⇒= inI ; ;

2

222

L

µm10

10

µA28

L

µm10Wµm10WL ==⇒= inI ;


Outline



• Advanced design techniques– Design for low-noise: active bridge example

– Design for robustness: digitally programmable current source

40

Case study: magnetometer signal conditioning

41

Reference resistors

Strain gauges

∆R

A×∆V

High power

consumption

∆R

mAIR

VI LNA

CCTOT 1>+=

Targeted power consumption : 100µA (for mobile applications) – less for autonomous systems

+−LNA

Vcc

gnd

Wheatstone bridge SNR

• For a given signal (∆R/R), SNRWB increases withVcc and reduces with R and BW

42

2

V

R

R

R2

R1

2

V

R

R

R2

R1

1

2

V

R

RV

RR2

RVV CCCCCC

CC∆≅

∆−∆=

∆+

∆=∆+

∆=− −+

∆R

A×(V+-V-)

∆R

+−LNA

Vcc

gnd

( ) kTR4VVVV

kTR2R

kT42

2

RVV

2n

2nn

nn

=+=−

=×==

−+−+

−+

( )

××∆

=

−×−=

−+

−+

BW.kTR16R

VRlog20

VVBW

VVlog20SNR CC

n

WB


29/04/2010

8

Output SNR and LNA’s noise figure

• LNA is necessary to reach a measurable signal

• LNA will amplify signal and noise of the WB

• LNA will add its own noise to the output

• LNA’s noise figure NFdB is used to characterizethe loss of SNR due to the LNA

43

∆R

Vout=A×(V+-V-)

∆R

+−LNA

Vcc

gnd

( )

××∆

=

−×−

=−+

−+

BW.kTR16R

VRlog20

VVBW

VVlog20SNR CC

n

WB

OUTWBdB SNRSNRNF −=

( )( ) kTR4VV

VVVAV

n

2nLNA

2nno

=−

+−×=

−+

−+

Output SNR and LNA’s noise figure44

• Preserve input SNR by having an amplifier withnegligible noise contribution

• Example : R=1kΩ and Veff=0,1V

• How to reduce power consumption?

nconsumptiopower large and V small

R

eff⇒==

>⇒<

eff

b

eff

dsatm

mm

V

I

V

I2g

R3

4g

g3

4

LNA)(WB +=⇒=> mW75,3PµA133VR3

4I effb

Outline



• Advanced design techniques– Design for robustness: digitally programmable

current source

– Design for low-noise: active bridge example

45

Documents

Cours Circuits Intégrés Analogiques - 2008/2009 - 29/04