Embedded ADC characterisation techniques

Embedded ADC characterisation techniques

J. Raczkowycz S. Allott

Indexing terms: Analysis technique, Data optimisation

Abstract: A novel data analysis technique for testing embedded ADCs known as data optimisation is presented that alleviates scan-path loading and, when used as part of a go/no-go test, reduces the amount of primary-test data and computer-time intensive operations to a minimum. To implement this test technique, a BIST scheme is presented which increases the control and observation of an embedded ADC, and enables real-time testing of an embedded 8-bit ADC with a 78% reduction in the amount of data needed to be shifted off-chip. Finally, comparisons between theoretical, modelled and practical results are made and appropri- ate conclusions drawn.

1 introduction

The growing complexity of mixed-signal VLSI architec- tures demands the use of embedded ADCs as on-chip digitisers [l], which aid in the testing of analogue macros via scan-paths [2]. However, the inherent controllability and observability problems [3] associated with the embedded ADC inhibits the application of the ADC test waveforms and the acquisition of the ADC test data, and thus demands an alternative testing technique to that used for conventional ADC analysis. This paper will show that a testing technique has been developed for embedded ADCs that overcomes the inherent control and observation problems, and hence improves the ADC testability.

The advantages of design-for-test (DFT) as a technique for testability improvements are well known within the digital VLSI community [4-71. The need for DFT within analogue and mixed signal circuits is also recog- nised and has resulted in several notable test techniques such as the use of complementary sequence sets [SI, hybrid built-in self-test (HBIST) [2], the analogue bus [SI, complementary signature analysis [lo], supply current monitoring [ll] and transient response analysis [12]. However, the diversity of analogue and mixed signal error classification and characterisation makes the advantages of any one technique less clear. It is the general consensus of opinion that a generic mixed signal testing strategy must consist of a combination of strat- egies with the overall aim of increasing the testability.

0 IEE, 1995 Paper 19266 (ElO), first received 13th October 1994 and in revised form 14th March 1995 The authors are with the Division of Electronics and Communication, The University of Huddersfield, Queensgate, Huddersfield, HD1 3DH, United Kingdom

I E E Proc.-Circuits Devices Syst., Vol. 142, No. 3, June 1995

2 Embedded ADC testing problems

The following testing problems and subsequent discussion and analysis are bound by the premise that the ADC is limited to Nyquist rate sampling. The characterisation of an isolated Nyquist rate ADC can usually be achieved by the application of a number of deterministic tests such as histogram analysis [13], FFT analysis [14], beat frequency analysis and envelope testing [IS]. Using these techniques, characterisation parameters such as linearity, missing codes, offset errors, gain errors and noise characteristics can be measured. To perform these tests on an ADC embedded deep within a mixed signal archi- tecture would cause a number of problems.

First, shifting vast amounts of output test data (in the order of 200000 samples for an 8-bit ADC histogram test) off-chip would be time consuming. Also, the need to shift this data off-chip would inhibit any on-chip scan- path use for the duration of the test.

Secondly, dynamic testing must be carried out at the ADC's maximum conversion rate. Hence, for effective characterisation, the output data would need to be shifted off-chip at n x the conversion rate of the ADC under test, where n is the resolution (in bits) of the ADC.

Finally, any test applied to the ADC would require a spectrally pure waveform to be presented at its input.

3

The problems associated with the testing of an embedded ADC can be categorised as control problems, due to the need for spectrally pure test waveforms, and observability problems, due to the large amounts of ADC output data and the generally fast ADC conversion rates [16].

The application of a spectrally pure test waveform to the input of an embedded ADC can present a number of problems. Two of the more important problems are now considered. First, the IC input pin may not have been connected directly to the input of ADC under test, this may distort or even eliminate the test waveform and thus make testing ineffective. Secondly, even if the IC input is connected directly to the embedded ADC input, the crosstalk noise picked up by the incoming test signal may degrade the signal to such an extent that it is no longer suitable for ADC test. The problems encountered when applying a spectrally pure test waveform serve only to degrade the controllability of an embedded ADC.

To overcome the control problems associated with the testing of an embedded ADC, some form of on-chip test waveform generator is required. This would eliminate the distortion of the test waveform by placing it close to, and connecting directly with, the ADC input. Also careful positioning and screening of the waveform generator would reduce crosstalk induced errors.

The test generator structure considered is known as a

145

BIST approach to embedded ADC test

pulse adaption macro (PAM). The PAM structure allows a triangular waveform to be accurately generated on-chip from a pulse sequence. A pulse sequence was chosen as the stimulus to the PAM as it can be easily transmitted through most mixed signal circuitry, hence increasing the controllability of the embedded ADC.

To overcome the test problems associated with the large amounts of ADC output data and fast conversion rates, a form of on-chip data compaction and buffering is required. Both these requirements are accommodated by the hardware shown in Fig. 1. Within Fig. 1, a form of data compaction is achieved by using a RAM structure and an incrementer cell (inc. c d [ ) at the ADC outputs.

boundary scan

scon control

measuring noise characteristics were considered, the details of which now follow. To eliminate the spikes present on a histogram plot due to the quantisation

boundary scon n scon control

data anolysis

I

(start)' 4 control ~ ~ $ r s i o n

\ \ / / \ \ I I - / I \ & /

re ister

w start

conversion

Fig. 1 Proposed data compaction circuit

This concept of on-chip histogram analysis was initially investigated by Bobba [l] who performed real time histogram testing of microcontrollers, and is extended here for use in VLSI integrated circuits.

Upon completion of the test, the data will remain in the RAM until a scan control signal is received. At this point the data will be transmitted to a serial scan-path, at a data rate dictated by the scan-path clock, and shifted off-chip. In this way a buffering facility is provided.

Once off-chip, analysis of the digital output data will be initiated via DSP software. The DSP software will implement a data analysis technique which aims to fully characterise an embedded ADC using only histogram analysis data. As the data analysis technique used optim- ises the information gained from one test (i.e. histogram analysis) it is termed data optimisation, and will be detailed in Section 4.

The overall BIST approach to embedded ADC testability improvement is illustrated in Fig. 2. The multi- plexer (MUX) seen within this Figure allows test waveforms to be generated on-chip via a PAM structure or applied directly through Ai,.

4 Data optimisation technique

The frequency response spectrum for any ADC can be obtained by applying a fast Fourier transform (FFT) algorithm to the digital output codes.

To perform spectral analysis on an embedded ADC is not feasible since, at present, the FFT machine required for this test would take up large amounts of silicon in comparison with the unit under test (UUT). Hence, due to the silicon restrictions mentioned, other methods of

146

Fig. 2 Proposed BIST approach to datu optimisation

process requires that a large number of samples are taken [13, 171 resulting in the quantisation effect being averaged out.

The elimination of the spikes due solely to quantisation within histogram analysis, unfortunately averages out all the noise information present on the signal. As a result, to date, histogram/probability analysis has not been used to measure ADC signal to noise ratios. However, if the number of samples taken within histogram analysis is limited, the quantisation and back- ground noise will not be averaged out and the histogram plot becomes highly sensitive to certain noise factors; acting on and within the ADC. By utilising this technique a relationship between the effect of noise on a histogram plot and the effect of noise on the ADC SNR can be established. Data optimisation is the establishment of this relationship.

5 ADCmodel

The data optimisation technique can be established by investigating the relationship between the signal to noise ratio (SNR) of an ADC and the effects of noise on its histogram plot. To aid in this investigation, a software based model of an ADC has been developed which allows a variety of ADC errors to be introduced. This model converts a continuous sinusoidal signal to equivalent discrete levels, where the conversion process takes account of various quantisation parameters such as linearity, offset, noise and jitter.

For modelling purposes the ADC is represented by a linear dynamic block, corresponding to a sample and hold (S/H), followed by a nonlinear static block, corresponding to the subsequent circuit stages. An illustration of the behavioural SAR ADC model used within the experiments can be seen in Fig. 3.

Within Fig. 3 the noise present on the dynamic stage of the model N , , may be assumed to be timii~g jitter and the noise present on the static stages N, , may be attrib- uted to quantisation distortion, input noise, noise arriv- ing with the input signal and noise coupled from the environment. The circuits modelled are assumed to be


tolerant of fabrication process variations and hence avoid the need to model a process sensitisation matrix.

dynamic stages I static stages

analogue input

ana loguec - - / DIA converter reference

d i g i t o m ' output f 1 shift register, control logic, status

(busy) start conversion

L 5erIo1 output b clock clock output

Fig. 3 SAR ADC model

Using the behavioural ADC model, Gaussian noise is referenced to the static ADC input and coupled with the ADC sample timing within the dynamic section, to produce jitter. To avoid ADC overload, the amplitude of the analogue input signal within the model is reduced from the full-scale value by 3u, where u is the standard deviation of the Gaussian noise. This reduction in amplitude allows the effects of noise to be monitored without introducing full-scale clipping errors. By applying a form of coherent histogram analysis to the resulting ADC output data the effect of ADC noise on the histogram plot is assessed. In general, when conventional histogram analysis is applied to ADC output data, thousands of samples must be taken to ensure accurate linearity measurements are obtained from the histogram data [18]. This high sample number will average out the noise information and, in our case, prohibit noises analysis. To avoid this averaging phenomenon, the number of samples N taken within the histogram analysis technique was reduced from 200000 to 2048. This reduced sample number was arrived at by an iterative process whereby the effect of noise on the histogram plot was increased whilst maintaining an acceptable SNR. In addition, coherent sampling was used to maximise the amount of information gained from each sample (by avoiding data repetition) and spread the noise information equally throughout the spectral range. To this end, the number of cycles A4 of the input sinusoid captured was set to 101 (such that the input test frequency is less than the Nyquist limit), resulting in a prime M to N ratio of

M 101 N 2048 -

5.1 Noise sensitisation coefficient A sensitisation coefficient, Aj [19, 201 is used to establish a link between the ADC noise and its effect on the histogram data. The Aj coefficient is defined as the difference between the histogram plot of an ideal ADC with a reduced sample number and the histogram plot of an ADC with a noise component ofj. Hence

where i is the code number (for an 8-bit ADC n = 256), and d is the modulus of the difference between the prob-

IEE Proc.-Circuits Devices SJW, Vol. 142, No. 3, June 1992

ability of occurrence of each code, such that

ideal frequency of occurrence total number of samples

d = l

nonideal frequency of occurrence total number of samples

-

The magnitude of RMS noise introduced to the ADC model is controlled by adjusting the standard deviation U. Dividing this RMS noise magnitude by the ADC's incremental step size V,,/2" gives the RMS noise value in LSBs, which is termed AV, where

where Vr, is the full-scale voltage of the ADC and n is the converter resolution, in bits. By analysing the relationship between Aj and AV, the sensitivity of histogram analysis to the ADC noise was assessed.

6 Simulation results

This Section presents and discusses the results of software modelling procedures to assess the Aj and A V relationships. The simulations within this Section were performed using a 2.4 kHz sinusoidal test signal where the amplitude of the test signal was adjusted according to the RMS noise voltage (as previously mentioned in Section 5). Although a sinusoid was used within these simulations, in general, any signal can be used as long as its statistical and spectral characteristics are known.

6.1 Noise effects on histogram analysis A graph of Aj against A V RMS noise (in LSBs) is shown in Fig. 4. This graph was obtained by modelling an 8-bit

o.05d OY 0 0-5 1 1.5 2

A V , LSBs

Fig. 4

ADC with no jitter or linearity errors, and illustrates the sensitivity of A j to the noise present in an ADC with ideal linearity.

6.2 Noise effects on the SNR Fig. 5 shows a graph of SNR against A V RMS noise. Again, this graph was obtained by modelling an 8-bit ADC with no jitter or linearity errors.

From the graph of Fig. 5, it can be seen that, when the noise added to the ADC model is zero (i.e. A V = 0), the maximum SNR is 47.5dB. Theory suggests a SNR of

Graph of A j uersus A V

147

approximately S0dB for an ideal device [18]. The dis- crepancy between these SNRs occurs as a direct result of the low sample number taken during analysis.

30. m U

n z m

20

35 -

30 - m

LL' ,$, 25-

U

20 -

I5 -

-

I

10

0 0.25 0.5 0-75 1 1-25 1.5 1.75 A V , LSBs

Fig. 5 Graph of SNR versus A V R M S noise

As the value of A V is increased from 0 LSB to 2.048 LSB, it is apparent, from Fig. 5, that the SNR drops. When the value of A V = 0.5 LSB, there is a 1 LSB uncertainty in the quantisation process (i.e. h0.5 LSB uncertainty about the ideal ADC transition point) resulting in a steep drop in the SNR.

6.3 SNRJA, relationship for varying AV The data illustrated in the graph of Fig. 6 shows the relationship obtained by modelling an 8-bit ADC with

-

2.048 LSE

O l I 0 0.05 0 1 0.15 02 0 25 0.3

Aj.LSBs

Fig. 6

148

Graph of SNR versus A, for varying AV

no jitter or linearity errors and a 2.5 dB SNR adjustment to account for the low sample numbers considered. The noise introduced to the ADC model, as with the simulations of Sections 6.1 and 6.2, ranged from A V = 0 to 2.048 LSB.

From analysis of the data used to produce the graph of Fig. 6, it is apparent that deteriorating ADC noise conditions results in greater Aj figures with poorer ADC SNRs. Furthermore, when the linearity of the ADC is ideal and there is no jitter present, the SNR drops off dramatically as Aj exceeds 0.2 LSB. This marks the dis- tinction between a good and bad device.

With reference to the earlier Aj/AV response of Fig. 4, a Aj of 0.2 LSB corresponds to a A V of 0.5 LSB which, as noted previously, results in a transition point uncertainty of 1 LSR and a corresponding dramatic SNR drop.

6.4 SNRIA, relationship for varying jitter The data illustrated in the graph of Fig. 7 shows the relationship for a modelled 8 bit ADC with no quantisation noise or linearity errors and no SNR adjustment.

35.

30

m

25 I

2ol 'I \ 3 75ns

15 0 0,062 0.124 0.186 0.248 0.31

A i . LSBs

Fig. 7 Graph ofSNR versus Aj for varying jitter

The jitter value introduced to the ADC model ranges from 0 to 75 ns. From analysis of the data used to produce the graph Fig. 7, it is apparent that, as the jitter becomes progressively worse (i.e. the uncertainty of the ADC sample timing becomes higher), the SNR reduces and the value of Aj increases. This illustrates the sensitivity of Aj to the jitter present on an ADC with ideal linearity.

6.5 Effects of linearity errors on the SNRIA, relationships

The graph of Fig. 8 illustrates the effects of linearity for a modelled 8 bit ADC with no jitter and A V ranging from 0 to 2.048 LSB. The linearity errors introduced in these simulatians are in the form of transition point deviations from the ideal transition points, and range from 0 to 1.08 LSB. It is apparent that, as transition point errors are introduced, the ADC linearity deteriorates and a


family of SNR/Aj graphs are produced. Also each incremental step of the transition point error is matched by a corresponding shift in the Aj/SNR characteristic. Upon

40

30 m 9 LL z Lo

20

10-

~

~

-

higher linearity error > O , * . , , L , ! . 8 . 1

higher linearity error --------------------------c

' O t

01 0 4 0.425 0.45 0.475 0.5 0.525 0.55 0.575

A J . LSBs Fig. 9 Graphs of SNRIA, for deteriorating jitter and linearity

From analysis of the data used to produce the graphs shown in Fig. 9, it is apparent that the relationship described by eqn. 5 is also true for SNR/A, relationships for varying jitter. From this, a SNRIA, relationship can be obtained by simulating an ADC for only one linearity,

I E E Proc.-Circuits Devices Syst., Vol. 142, No . 3, June 1995

and shifting the resultant data left or right by an appro- priate amount dictated by eqn. 5.

Using the graph of SNR/Aj for deteriorating noise conditions, shown in Fig. 8, in conjunction with the graph of SNR/Aj for deteriorating jitter, shown in Fig. 9, a value for the SNR of an ADC can be obtained by measuring a value of Aj and obtaining a figure for the ADC transition points, which identifies the correct characteristic graph. The ADC transition points can be calculated from the histogram plot data using a cumulative histogram [13] according to the equation

- A cos (7) nCH(i)

TPALSB) = VJ,/2"

where

T P , = the transition voltage of code i A = the sinusoidal amplitude

N , = the total number of samples. CH(i) = the cumulative histogram

For practical ADC go/no-go testing purposes, the minimum SNR can be set for a 'pass' ADC and, by noting the Aj, the SNR can be read off directly. Depend- ing on the SNR value read off the graph, the ADC is then labelled 'pass' or 'fail'.

7 Practical results

To substantiate the SNR/A, relationship, which is the basis of the data optimisation testing technique, an analogue device AD7575 8-bit SAR ADC was used as a test vehicle. By applying coherent histogram analysis to the output data of an analogue devices AD7575, a figure for the maximum transition point error, calculated using eqn. 6, was found to be 0.51 LSBs. This figure of 0.51 LSBs was then used to select the correct characteristic graph, from Fig. 8 and 9, to represent the ADC, which is shown in Fig. 10.

0.4 0-41 0.42 0.43 0.44 0.45 0-46 0 4 7 Aj,LSB

Simulated characteristic for AD7575 test vehicle Fig. 10

149

From analysis of the simulation data used to produce the graphs illustrated in Fig. 10, the S N R of the modelled AD7575 was measured to be 42.02 dB with a corresponding Aj of 0.424 LSB. This simulated S N R measurement is approximately 3 dB lower than the value obtained from the ADC data sheet, which indicates a minimum S N R of 45 dB. This is, however, consistent with the results of Section 6.2 which indicate an overall S N R drop due to the reduced sample number taken within analysis.

To substantiate the results from the ADC model described in Section 6, the effects of noise within a practical ADC must be analysed. The analogue devices AD7575 8-hit SAR ADC was once again chosen as the test vehicle. The hardware illustrated in Fig. 11 was used

1 I RGlnoise HP 3245A I I generator untversol source ,

_ _ _ _ _ _ _ _ _ _ _ _ _ _ - _ _ _ _ _ _ ~~

I I I I I I I 1 I I I 1

I I

HP 8568A spectrum analyser

I Fig. 11 Data optimisation hardware

to analyse the effects of noise and jitter within the practical ADC. This hardware is split into four sections: section A is a low noise mixer (3.47 x W of extraneous noise power) and is used to introduce noise (equivalent to AV) to the ADC, section B is the sample timing circuit and is used to introduce jitter to the ADC (range: 3.4-52 ns), Section C is the DAC circuit (relative resolution to ADC: $ LSB) and is used to convert the digital data from the ADC to the analogue domain (from which, real-time noise analysis may be performed on the resulting DAC output by using a spectrum analyser), Section D is the BIST hardware and is used to measure A,. Section D consists of a Xilinx FPGA, designed for histogram control, and 8K of RAM, for data storage.

7.1 Full validation system results Using the full validation system previously illustrated in Fig. 1 1 , noise and jitter were introduced during the quantisation of a 2.4 kHz, 5 V, sinusoidal test signal. This bipolar signal is adjusted in amplitude to tolerate the R M S noise levels and is then converted to a unipolar signal in the range 0-2.46 V and input to the ADC (using this technique 1 LSB (ideal) = 39.06 mV). From the resultant digitised data, corresponding values of Aj were measured using histogram analysis with 2048 data points. In parallel with the Aj measurement procedure, the S N R measurements of the reconstructed waveforms were

I50

obtained from the HP8568A spectrum analyser. From these practical S N R and Aj measurements, the graph shown in Fig. 12 was produced.

15

5- 0.4 041 0.42 0.43 0.44 0.45 0.46 0-47

Aj ,LSB

Practical S N R versus A, results Fig. 12

The graph of Fig. 12 was obtained by introducing noise (AV) ranging from 0.15 LSB to 2.048 LSB and jitter ranging from 3.4 ns to 52 ns (approximately - 18 dB to + 3 dB). This graph shows that any increase in Aj results in a reduction of the measured signal to noise ratio.

To verify the consistency of the SNR/Aj results for, practical ADCs, four additional AD7575s were tested, using the procedure described previously within this Section. A comparison of the SNR/Aj results from the four AD7575s and the SNR/Aj relationship for the test vehicle can be seen in Fig. 13. From this comparative test a high correlation is observed between the SNR/A, relationships. This suggests that the results obtained, within this Section, apply (to a close approximation) to any generic AD7575 ADC.

8 Discussion of results

A comparison between the AD7575 simulated SNR/Aj results and the practical SNR/Aj results obtained using the validation system described in Section 7 is illustrated in Fig. 14. This graph shows discrepancies between the practical results obtained from the validation system and those obtained from the ADC model at levels of Aj above 0.4425 LSB. These discrepancies,which are still being investigated, may be due to the complex interaction of noise and hitter within the ADC together with variations in ADC gain and offset. For the purposes of validation, however, these discrepancies do not discredit the data optimisation testing strategy, as Aj figures above 0.4425 LSB represent a failed device regardless of its S N R .

For Aj figures in the region 0.39 LSB to 0.4425 LSB, the simulated results matched those obtained in practice and, as a consequence, can be used to effectively characterise an ADC in terms of its S N R .

Section 7.1 presented a comparative test of the SNR/Aj characteristics for five ADCs (four AD7575s and

IEE Proc.-Circuits Devices Syst., Vol. 142, No. 3, June 1995

the test vehicle). From the results of this test, it is clear that, although the effects of fabrication tolerances are small, a tolerance of A j and SNR must be observed to

45

40

m D

z m rr 35-

30

-

-

-

251 I 0.41 0.42 0.43 0.44 0.45

A J , LSBs

Fig. 13 Comparison ofSNRIA, relationships ~ AD1515 test vehicle

four ADlS75s ~-~~

m

E. V

z m

0.41 0.42 0.43 0.44 0-45 0.46 0-47 AJ.LSBS

Fig. 14

I E E Prof.-Circuits Devices Syst., Vol. 142, No . 3, June 1995

Comparison of simulated and practical SNRIA, results

avoid good ADCs failing the data optimisation test. However, to estimate these tolerance values from five devices would be unwise.

8.1 Data optimisation versus conventional analysis Consider applying a go/no-go test to an embedded ADC, which has identical characteristics to the AD7575 test vehicle, using both data optimisation and conventional analysis techniques. Using comparative analysis the following points can be ascertained.

8.1 . I For an ADC that fails the golno-go test: The data optimisation routine fails this ADC with 6144 less data points than conventional analysis (assuming 8192 data points are used for linearity measurements).

8.1.2 For an ADC that passes the golno-go test: Con- ventional analysis tests the ADC with 4096 less data points than the data optimisation technique. This means that 2048 less data points are required for the data optimisation technique than for conventional analysis.

Data optimisation only shifts 256 x 2 samples off- chip, compared to 2048 + 256 for conventional spectral analysis.

Data optimisation requires a scan path with the speed of that required for conventional analysis.

Once off-chip, the data optimisation method of analysis can characterise the ADC, in terms of noise, by comparing the Aj value against a computer 'look up' table. Whereas conventional analysis must perform an FFT then measure the SNR, which is a much slower process.

9 Conclusions

The applicability of dynamic ADC characterisation techniques to the testing of embedded ADCs has been criti- cally assessed. The results of this assessment demonstrate that, due to the poor control and observation of embedded ADCs, efficient testing demands a BIST approach, and the only test applicable to BIST implementation is histogram analysis.

When used as a go/no-go test, the data optimisation test technique keeps the amount of primary test data to a minimum (2048 data points for an 8-bit ADC). This is important as it reduces the amount of time spent testing potentially faulty devices.

Using data optimisation, the ADC noise characteristics can be calculated in less time than for conventional analysis. This is because the computer-time intensive operations are performed prior to testing. Furthermore, using data optimisation, an 8-bit SAR ADC can be characterised, in terms of linearity and noise, with 20% less data points than needed for conventional analysis. The importance of the reduced data and analysis time is seen in production test, where ICs must be tested as quickly as possible, but with no reduction in test accuracy.

To complement the data optimisation test technique a BIST scheme has been presented (Section 3) which util- ises a RAM (of length 2" locations, where n is the resolution of the ADC under test) and a PAM structure. This BIST scheme increases the control and observation of an embedded ADC, and provides a data compaction facility that reduces scan path loading by l jn , where n is the resolution of the ADC in bits. The reduction in scan path loading is important as it encourages parallel testing of other sections of the IC whilst the ADC is being tested.

151

Furthermore, when utilised as part of the data optimisation technique, the BIST hardware allows real time testing of the ADC with a 78% reduction in the amount of data needed to be shifted off-chip.

The overall effect of data optimisation is that testing times, and ultimately production costs, will be minimised.

9.1 ADC modelling All the converter noise within the ADC model is referred to the ADC input and is assumed to be uniformly distrib- uted over the full noise bandwidth of the unit under test.

From the results obtained and described within this paper, it is expected that any embedded ADC can be suc- cessfully characterised using the data optimisation method of test in conjunction with the BIST scheme of Section 3 and the ADC model of Section 5.

10 References

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3 MARKOWITZ, M.C.: ‘Design for test (without really trying)’, EDN, 1992, pp. 115-126

4 McCLUSKEY, E.J.: ‘Built-in self test techniques’, IEEE Design Test Cornput., 1985,2, (2), pp. 21-28

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of papers, semiconductor test symposium, 1971, pp. 6-15 6 STEWART, J.H.: ‘Future testing of large LSI circuit cards’. Digest

7 ANDO, H.: ‘Testing VLSI with random access scan’. Digest of papers, Compcon ’80,1980, pp. 50-52

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10 Schreiber, H.H.: ‘Fault dictionary based upon stimulus design’, IEEE Trans., 1979, CS-26, pp. 529-531

1 1 CAMPLIN, D.A., BELL, I.M., TAYLOR, G.E., and BANNISTER, B.R.: ‘Can supply current monitoring be applied to the testing of analogue as well as digital portions of mixed ASICs?’, IEEE Proc., 1992, pp. 538-542

12 TAYLOR, D., EVANS, P.S.A., and PRITCHARD, T.I.: ‘Develop- ment of eeneric testing stratedes for mixed simal ICs’. IEE Proc. G , 1992,139, pp. 231-233 -

13 DOERNBERG, I., HAE-SEUNG, L., and HODGES, D.A.: ‘Full speed testing of A p converters’, IEEE J., 1984, SC-19, (6), pp. 820- 827

14 EVANSON, D., and MUS’HING, A.: ‘Performance testing of high speed A/D converters’, Electr. Eng., 1988, pp. 35-42

15 ‘Dynamic performance testing of A to D converters’. Hewlett Packard product note 518OA-2

16 ALLOTT, S., and RACZKOWYCZ, J.: ‘The characterisation of embedded analogue to digital converters’. Second international conference on advanced A-D and &A conversion techniques and their applications, 1994, pp. 163-168

17 KESTER, W.: ‘Measure flash-ADC performance for trouble free operation’, EDN, 1990, pp. 103-114

18 MAHONEY, M.: ‘DSP based testing of analog and mixed signal circuits’ (IEEE, Computer Society Press)

19 ALLOTT, S., and RACZKOWYCZ, J.: ‘Optimization of mixed mode testing using novel pulse adaption technique’. ICSSICT, CHINA, 1992, pp. 397-400

20 ALLOlT, S., and RACZKOWYCZ, J.: ’The improvement of observation and characterization techniques applied to embedded analogue to digital converters’. IEE colloquium on testing mixed signal circuits, 1992, Digest 1992/118, pp. 7/1-7/3

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Embedded ADC characterisation techniques