Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive

Voltage Level Controller

An Alternative to Clock-Gating Scheme in Leakage Dominant Era

1,2Kyeong-Sik Min, 1Hiroshi Kawaguchi, and 1Takayasu Sakurai

1University of Tokyo, Tokyo, Japan2Kookmin University, Seoul, Korea

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Outline

� Introduction� Zigzag Super Cut-off CMOS (ZSCCMOS)� ZSCCMOS Block Activation� Control Circuitry with Adaptive Voltage Level

Detector� Measurement & Discussion� Summary

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Previous Leakage Suppression Scheme: Super Cut-off CMOS (SCCMOS)

� Full swing of �L� nodes and VSSV nodes at wake-up => Long wake-up time and high rush current at wake-up

�L� nodes & VSSV(changed during

sleep & restored to VSS at wake-up)

VDDVDD

�L��H��L� �H�

VSSV

Cut-off SWActiveSleep

VGN VSS

Wake-up

�H� nodes(not changedduring sleep)

VGN

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Zigzag Super Cut-off CMOS (ZSCCMOS)

�H��L�

VSSV

VDDV

�L� �H�

Cut-off SW

Cut-off SW

Sleep Active

VSSV

VGN VSS

VDD

VGN

VGP

VDDV

�H��L�

� Small voltage change of VSSV and VDDV due to reverse-source biasing effect�No voltage change of �H� and �L� nodes at wake-up=> Short wake-up time and low rush current at wake-up

Wake-up

-0.3V reducing leakage to ~1/1000

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Derivative of ZSCCMOS (ZBGMOS)

Sleep Active

Pumpclock

VGN VSS

VDD

�H��L�VSSV

VDDV�L� �H�

VGN

VGP

�H��L�VSSV

VDDV�L� �H�

VGN

VGP

Sleep Active

Pumpclock

VGN VSS

VDD

High VTHThick Tox

� Not consuming pumping power during sleep © 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Low-

leakageF/F

VDDV

VSSV

�L� �H� �L�

ZSCCMOS Block Activation Scheme with Phase Forcing

D0

D1

In0

In1PFPF F/F

Phase forcing(PF) circuit

� Forcing every node to be �L� or �H� at sleep

�L��H�

PF�H��L�

SLEEPACTIVE

ForcedInternalnodes

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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LCLK

INV with high VTH

VSSV

VDDV VDD

VSS

Low-Leakage Flip-Flop

D(�H�) Q(�L�or�H�)P(�L�)

G2 G3

VGP

VGN

CKCKB

To other

blocks

� Node Q not to be forced to �H� or �L�during sleep� High-VTH INV not on the critical path

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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VBIAS

Self-AdaptiveVoltage Level Detector (SAVLD)

Oxide-stress-relaxedlevel shifter

IREF

MN2

VLDO

Control Circuit for NMOS Cut-off Switch

To controlchargepump

VNW2/L

Logicblock

Cut-off SWMN1VGNW1/L

ILEAK

� Self-adaptively adjusting VN as

Startpump

Stoppump

VLDO

VN

∆VN

REF12

LEAK IWWI =

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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1.1V

30mV∆VP

VLDO

VDD=1.1V

Measurement of Self-Adaptive VP Level Detector

� Fabricated in 0.6-µm CMOS N-well process� Self-adaptive VP adjusting with varying temperature

25 50 75-0.2

-0.1

0.0

0.1

VDD=2V

MeasurementSimulation

V Psh

ift (V

)

Temperature (ºC)

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Measurement Set-up

IN OUT IN

OUT

IN OUT IN

OUT

SCCMOS

ZSCCMOS

TWake-up

TWake-up

Measured by21-Stage ROSC

To avoid high-voltage stress

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Comparison of Measured Wake-up Time

� Fabricated in 0.6-µm technology� 8 times shorter wake-up time of ZSCCMOS than SCCMOS

1 2 3 40.1

1

10

100

ZSCCMOSSCCMOS

Simulation

Wak

e-up

tim

e (n

s)

VDD (V) T=25ºC

1.0WW

circuitTotal

SWoffCut =−

F.O.=3 INV

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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� Simulation by assuming 70-nm technology using Berkeley Predictive MOSFET Technology Model (BPTM) � 12 times shorter wake-up time of ZSCCMOS than SCCMOS

Comparison of Simulated Wake-up Time

WCut-off SW/WTotal circuit

T=25°C VDD=0.6V

0.00 0.04 0.08 0.12101

103

105

107

ZSCCMOS

SCCMOS

Wak

e-up

tim

e (p

s)

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Test Chip Micrograph

� Fabricated in 0.6-µm CMOS technology

I/O Buffers

Ring configuration to measure wake-up time

I/O B

uffers

VP

generator

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE

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Summary

� Zigzag scheme presented for leakage dominant era

� ZSCCMOS: ~200-ps wake-up time andsmaller rush current than SCCMOS

� ZSCCMOS block activation schemereduces leakage power to ~1/1000 when inactive.

� Gate voltage of cut-off SW self-adjusted so as to set ILEAK constant over PVT variation

© 2003 IEEE International Solid-State Circuits Conference © 2003 IEEE