Activités Microélectroniques sur LSST

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Activités Microélectroniques

sur LSST

Hervé Lebbolo pour le groupe LSST électronique LAL / LPNHE

Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

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Telescope and site : Cerro Pachon, Chile

LSST : Large Synoptic survey Telescope

Temps de pose : 15s Lecture : 2s


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CRYOSTAT

Plan focal & Rafts

TOWER• CCDs + front end

electronics• 180K operation• An autonomous, fully-

testable and serviceable 144 Mpixel camera

RSA

RCC

FEC

RAFT• 9 CCDs• coplanarity

13.5mm• 92% fill factor

4K x 4K CCD• 10mm pixels = 0.2”• extended red response• 16 outputs• 5mm flatness

4 cm

3X3 CCD

64cm3.5°

21 rafts, with 9 CCDs eachCCD : 16 * 1MpixelCamera : ~3Gpixel


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Chaîne de lecture de la caméra

18 bit

ADC

CABAC

ASPIC : Analogue Signal Processing Integated CircuitCABAC : Clocks And Biases Asic for CCDReadout : 500kHz

RCM


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8 channels dual slope integrator Operates @ 173K CCD readout @ 550kHz – up to 1MHz Power dissipation : 25mW / channel Power Supply 0/5V with respect to reference = 2.5 V Noise :

~5nV / √Hz maximum noise density [ 5 to 6 e- read noise (10nV/ √ Hz) for the whole CCD chain]

7µV rms for 500ns integration [< 2 e-]

Crosstalk : 10-4 level [ 0.01% (goal) - 0.05% (max) ] Full Well capacity :

90keˉ [150keˉ max] ie ~400mV max input Linearity : 0.5% [defined over to full well scale] Differential outputs Output Load : 50pF // 1 k Ω Nap mode

ASPIC Requirements


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CCD Reset

ASPIC Reset

CCD Output

Integration TimeTint

Isolation Time

ADC S/H

Dual Slope Integration sequence

One of the 2 differential channel output

Ramp Down(integrate noise)

Ramp Up(integrate signal + noise)

Read Out Method : Dual Slope Integration


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ASPIC (2)

3 programmable input amplifier gains : 2.5 – 5 – 7.5

to deal with CCD gain spread.

3 integration time constants : 500ns – 1µs – 1.5µs

to deal with CCD readout frequency.

baseline : {gain 5 & 500ns integration time}

Input amp


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Schéma de Base


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ASPIC 2 layout

• Techno : CMOS 0.35µ 5V • Vendor : AMS

• Package 1 : CQFP100

• Package 2 : QFN100 avec bottom pad pour un meilleur contact thermique

• Surface : 2,7*3,8 mm²


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ASPIC2 tests bench

Front EndBoard

(cryo or roomtemperature)

CustomBack End

Board(8*18 bit ADC Altera FPGA)

PC+

LabView

generators

ProgrammablePower Supplies

ASPIC (2)

Sw

itch

es

Board

Programmmable

attenuator

signal

ck

127dB / 1dB step


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USB

FIFO

External trigger

ADC channel

FPGA

Input (from ASPIC)

Output to ASPIC :clocks,

commands

Gain switches

Output to CCD

Back End Board


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Cold Front end (LPNHE)

Flex cable and 37-pin connector (17 grounded)Shielding with thermal break (mesh)

Temperature sensors & heating

Outputs and power supply

Clocks and settings

Inputs

4 CCD inputs

Cooling: front-end card connected to nitrogen circuit


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LAL Cold Test Stand

QFN PackagingWith bottom pad

Sub Micro D connectors8 input Clamp for X talk measurements


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Nominal Gain

Measured Gain

Post layoutSimul*.

2.5 3.9 4

5 6 5.9

7.5 7.8 8

Chip-to-chip rms dispersion = 2%

In-chip dispersion rms dispersion = 0.3% on average – 0.5% at most

ASPIC II Measurements : Gain

Gain measured over 37 chips

*: R&C extraction


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0 100 200 300 400 500 600 700 800

0

5

10

15

20

25f(x) = 0.031x - 0.344

f(x) = 0.024x - 0.273

f(x) = 0.016x - 0.200

Effective GainNominal RC = 500 ns

2.5Linear re-gression for 2.55Linear re-gression for 57.5Linear re-gression for 7.5

Integration time (ns)

Tota

l gain

ASPIC II Measurements : Gain


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Effect of input amplifier bias

ASPIC II Measurements : Noise

le bruit peut être encore diminué si le budget puissance augmente


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gain=5 (6), RC=500ns residu: 0.3%

ASPIC 2 Linéarité

gain=2.5 (3.9), RC=500ns residu: 0.4%

residu (data fit)datamax

Requirement : < 0.5 % over full well range Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

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Measurements : Crosstalk

Y axis = sourceX axis = victim

Xtalk asymetric : injecting a signal in the ch 7 generate more crosstalk than injecting a signal in the ch 0.

When the ASPIC II input stage saturated, the Xtalk also saturates : Xtalk is probably dependant of the amplitude at the output of the first

amplifier.

Notice: postlayout simulations don’t show any crosstalk effects.ASPIC I had a smaller Xtalk ( < 0.007 % ) than the ASPIC II and no programmable gain.


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Effect of the integrator reset width on the channel memory

Effect of the integrator reset width on the channel memory

150ns 200ns 250ns

Measurements : Memory


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• Mesure de la réponse à un niveau DC : efficacité de l’annulation du bruit de reset (kT/C) du CCD et de la dérive du signal d’entrée (couplage AC)

• Asymétrie : 0,07% ( bruit de reset CCD : 60 e⁻ erreur 0,04 e⁻)

• Asymétrie totale ~ asymétrie gains * asymétrie intégration

ASPIC2 TESTS DC Asymétrie

ASPIC input

G+

G-

S+

S-

Different gain / Same Time Constant

Ramp down Ramp up

Difference = 0


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• Tests à froid sur long terme : vieillissement ? dégradation des performances ?

• Mesures plus fines des effets mémoire, Xtalk, impact des temps d’isolement sur le bruit

• Mesures avec le CCD250-------------------------

• Augmentation du « gain » et du full well (150ke) du CCD d’e2v

• diminution du gain (augmentation du bruit)• Programmation plus fine du temps d’intégration et du

gain (2*4bit)• Mode transparent (monitoring des signaux CCD)• Sonde de température ?• Programmation par lien série• Amélioration de la vitesse de « réveil »

ASPIC 2 suite et fin ASPIC 3


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ASPIC 3 suite

Mode transparent

Soumission prévue début 2013


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CABAC : clock and biases asic for CCD

IΦ0

IΦ1

IΦ2

IΦ3

IΦ3

Fournir les horloges (série et parallèle), les polarisations et les alimentations des amplis de sortie des CCD


CCD requirementsOD &Biases e2v CCD250 ITL/STA1920A HPK S10892-03

expose readout erase

Back substrate BS -70 BB -10 VBB 50 30 0,2

Front substrate FS 0 SUB 0 VGR 0 0 0

Guard GD 30 SC 16 - - - -

Output Drain VOD 30 OD 27 VOD -5 -20 -5

Output Gate VOG 2 OG -2 VOG -5 -5 -5

Reset Drain VRD 18 RD 15 VRD -5 -12 -5

Test inject source - - - - VISV -5 -12 -5

Test injectgate - - - - VIGV 0 0 0

Clocks HI LO HI LO HI LO erase

Parallel 9 0 4 -11 -5 3 6

Serial 10 0,5 4 -4 -6 3 6

Reset Gate 9 0 10 -2 -6 5

Summing Well - - 4 -4 -6 5

Transfer Gate - - - - -5 3

Capacitances (estimated)

Parallel per phase 64 nF unavailable 25 nF (2K x 1K device)

Serial per phase 320 pF unavailable 50 pF

RG unavailableunavailable

10 pF

SW - - - - 10 pF

TG - - - - 100 pF

baseline

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CABAC requirements

• OD and Biases: – 2 OD : 8 bit programmable level from 13 to 36V, 16 mA capability each,

exposure & readout levels, load : 100Ω + .1µF

– 1 RD : 8 bit programmable level from 13 to 36V, 1kΩ + .1µF load, electronic calibration pulser

– 1 GD : 8 bit programmable level from 13 to 36V, 1kΩ + .1µF load

– 1 OG : 8 bit programmable level from 0.1 to 4.8V, 1kΩ + .1µF load

– 1 spare0 : 8 bit programmable level from 13 to 36V, 1kΩ + .1µF load

– 1 spare1 : 8 bit programmable level from 0.1 to 4.8V, 1kΩ + .1µF load

• Clocks : – 4 parallel, 8 bit programmable current capability (max 300mA),

common voltage rails (ΔV = 20V max), exposure/readout modes (static current divided by 10)

– 4 serial, 8 bit programmable current capability (max 16mA), 2 voltage rails (3+1) (max 20V), exposure/readout modes


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CABAC requirements

• Readout & Exposure modes input independant from serial programing

• Temperature sensor (current source + diode connected mos transistor)

• Multiplexor : Possibility to output 2 of any signal provided by CABAC or external input for monitoring, output can be disabled for paralleling

• Operates at 173K (?)

• Programmation by serial link with read back & asynchronous reset


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Process

• Process : AMS CMOS 0.35µm 50V, H35B4D3• Care has to be taken on Vgs for lifetime

(LTacc)• Durée de vie = 10 ans/LTacc

• Cryo temp lifetime : no guarantee from AMS


Prog

Serial link

// &SerialClocks

OD&

Bias

Calibpulser

Multiplexeur

From CCD, Aspic, FEB

Timing

Synoptique

CABAC Vers CCD

Vers BEB

From BEB

Tem

p

Power Supply

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8 bit DAC VCCS

Current mirror

Current mirror

LVDSreceiver

Leveltranslato

r

Clock Switch

VDDupper

VDDlower

Current setting

LVDSclock

Clocks

Exp/Ro

VDD command

Clock


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Clocks scheme


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Parallel Clock scheme


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Parallel Clock layout


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Readout settingregister

OD (& biases)

Voltage Amplifier

OD VDD

Exp / RO

8 bit DAC

Exposure settingregister

OD


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OD<0>, OD<1>,RD, OG

GD, Spare<0>,Ext<0>, Ext<1>

Serial <2:0>, RG

Parallel<3:0>

OD<0>, OD<1>,

Ext<5:4>Temp, Spare<1>,Ext<2>, Ext<3>

Serial <2:0>, RG

Parallel<3:0>

2:1 Mux

2:1 Mux

Out 0

Out 1

Dual 16 to 1 multiplexer

8 : 1 Active Mux

8 : 1 Passive

Mux

8 : 1 Active Mux

8 : 1 Passive

Mux


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Electronic Calibration Pulser implementation :

Pulser

CCD

trig

To aspic

Reset

RD

RD

calibpulse

Pulserenable

CABAC


36Hervé Lebbolo - Journées VLSI - Lyon - 07/06/2012

IΦ0

IΦ1

IΦ2

IΦ3

IΦ3

Resetcalibpulse

Electronic Calibration Pulser implementation :

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Serial link : Place & Route

~570*570µm²


Full Cabac_0 layout

Area : ~36mm²

TEST_0• AMS HV CMOS chip for HV & Cold

tests purpose• 5 mos transistors :

• 1 large (5000*3) 20V thick oxyde Pmos• 1 large (5000*2) 20V thick oxyde isolated

Nmos• 1 (100*3) 20V thin oxyde Pmos• 1 (100*2.5) 20V thin oxyde isolated Nmos• 1 (100*3) 50V thick oxyde Nmos

• One high level bias with 8 bit DAC• One temp sensor

TEST_0 layout

Area : 5.4mm²

10 chips packaged in QFN36

15 naked dies

Sent early november

Delivred in february

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TEST_0 test bench

TEST_0PCI

DIO 96

HostProgrammablePower Supply

RelayBoard

prog

usb

Scope

Vds, Vgs

AmmeterKeithley

Id, Ib

Vbias,..


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TEST_0 tests

Keithley

ProgramablePower supplies

Relay board

Hot tests board



Transistors tests

Keithley

Alim_P_source (0-20) Alim_N_drain (0-20)

Alim_N_gate (0-4)

Alim

_P_

Gat

e (0

-3,1

)


CABAC test bench

CABACTest FE

Capacitors

AnalogDigital

DaughterBoard

FPGAEvaluation

Board

Ethernet/usb

Host

hot

Hot/cold

hot

Scopes

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ADC série 18b 1MS AD7982

(x13)

CABAC Tests Bench

AlteraEP3C120

Ethernet GEDEK

OD

Mux Out<1..0>

OD<7..0>

Spare<1..0>GD OG RD

13SDO

RO/Exp& Serial Link

HSMC-B

Analog daughter board FPGA cyclone III dev board

2 SCOPES 4 channels + external trigger (WaveAce224)

Trigger SMA out

18

CNVSCK

Trigger_extTrigger_out

ADC série 16b 6MS

AD7625 (x2)

2SDO2CNV2SCK

2

15

12

DAC 0

SCLKSYNC

SDINDAC nDAC 6

SDO

BIAS

4

MUX

CABAC8ck / 1pul

9p

CK

CABACLVDSCMOS

7

30 pinsLVDS

(15 pairs)

28 pins 2.5V-LVCMOS


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The End


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Activités Microélectroniques sur LSST