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COMPUTER ORGANIZATION, ARCHITECTURE & ASSEMBLYLANGUAGE

LECTURE 1

Review:

I. Data Representat!n

Bts – 0’s and 1’s Word – 16 bitsB"te – 8 bits Doubleword – 32 bitsN##$e – 4 bits Quadword – 64 bits%!r – 16 bits Paragraph – 128 bits

II. N'(#er S"ste(

Binary Number System- has a base o 2!

- digits are 0" 1- a series o 1’s and 0’s

Decimal Number System- has a base o 10!- digits are 0" 1" 2" 3" 4" #" 6" $" 8" %- the nu&ber s'ste& used b' hu&an beings or (ounting

Octal Number System- has a base o 8- digits are 0" 1" 2" 3" 4" #" 6" $

- ea(h digit is (o&posed o 3 bits

Hexadecimal Number System- has a base o 16- digits are 0" 1" 2" 3" 4" #" 6" $" 8" %" )" *" +" D" ," - ea(h digits is (o&posed o a nibble

INTRODUCTION

C!(p'ter Ar)*te)t're

- reers to attributes o a s'ste& .isible to a progra&&er or attributesthat has logi(al i&pa(t on the e/e(ution o the progra&!,/! nstru(tion sets" the nu&ber o bits used to represent .arious

data t'pes" &e(hanis&s and te(hniues or addressing&e&or'!

Computer Architecture is built on our basic viewpoints

1! Structure – deines the inter(onne(tion o .arious hardware(o&ponents!

2! I mplementations – deines the detailed design o hardware(o&ponents

3! !erormanc e –spe(iies the beha.ior o the s'ste&!

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4! Or"ani#ation – deines the d'na&i( interpla' and &anage&ent o the.arious (o&ponents!

COMPUTER ORGANIZATION- reers to the operational units and their inter(onne(tions that realie

the ar(hite(tural spe(ii(ations!,/! hardware details transparent to the progra&&er su(h as (ontrolsignals" intera(es between the (o&puter and the peripherals and the&e&or' te(hnolog' used!

GENERAL ORGANIZATION O- A COMPUTER SYSTEM

D)5) *7

)DD,77 *7

E$e(ents ! a C!(p'ter S"ste(

1. Centra$ Pr!)essn/ Unt 0CPU - (ontrols the operation o the (o&puterand peror&s its data pro(essing un(tions" reerred to as the pro(essor!

2. Man Me(!r" – or data storage

3. Inp't+O'tp't 0I+O De4)es – &o.es data between the (o&puter and itse/ternal en.iron&ent!

5. S"ste( Inter)!nne)t!n – so&e &e(hanis& that pro.ides (onne(tion or(o&&uni(ation a&ong +P" &ain &e&or' and !

S"ste( B's - wires and printed (ir(uit board 9P+*: lines! t is the ph'si(alpathwa' that lin;s the (o&ponents o the (o&puter s'ste&!

t (an be<• nidire(tional – with onl' one low= ro& the +P to the

&e&or'!

• *i-dire(tional – happens i there is handsha;ing!

7'n(hronies the de.i(es o the &i(ropro(essor!

a. Data B's - it is bi-dire(tional 9(an be inout:- transer data between pro(essor" &e&or' 9data: > e/ternal

de.i(e!

#. Aress B's - address signal is sent irst" (o&ing ro& the&i(ropro(essor!- it (arriesholds address signals (o&ing ro& the

&i(ropro(essor or the &e&or' or unit!

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?P5D,@+,7

5P5D,@+,7

*, +P A,AB

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- unidire(tional!

). C!ntr!$ B's - nidire(tional - holds the (ontrol signals needed or s'n(hroniation o the

operation o the &i(ropro(essor! 9A" D" W:

PROCESSOR+CPU- brain o the P+ based on ntel 8086 a&il' that peror&s all

e/e(uting o instru(tions and pro(essing o data!

H/*$/*ts ! t*e e4!$'t!n ! t*e M)r!pr!)ess!r

ENIAC ,le(troni(s ?u&eri(al ntegrator and +al(ulator

5he irst general purpose progra&&able ele(troni( (o&puter

s'ste&= de.eloped in 1%46 at the uni.ersit' o Penns'l.ania! 100"000 P7= 30 5ons

5665 World’s irst &i(ropro(essor

4 – bit Ai(ropro(essor

4# in(hes set

sed in (al(ulator 9C"-:" .ideoga&e 9shuleboard:

4; 9&e&or':= #0 P7 E;ilo instru(tionsse(F 7peed= Gess that an

oun(e 9weight:5656

pdated .ersion o the earlier 4004

sed in s&all (ontrol s'ste&s!

66 91%$1: an e/tended 8-bit .ersion o the 4004 &i(ropro(essor

16;ilob'tes 9&e&or':= 48 instru(tion sets!

66 91%$3: the irst o the &odern 8-bit &i(ropro(essor

10 ti&es aster than the 8008!

,)GB 8-*it Ai(ropro(essor

Man'a)t'rer M!e$air(hild 8ntel 8080A7 te(hnolog' 6#02Aotorola A+6800?ational 7e&i(ondu(tor AP – 8o(;well nternational PP7 – 8Hilog H-8

67 91%$$: inter (lo(; generator in ter&s o I

ses (r'stal or reuen(' generation= higher (lo(; reuen('!

68

91%$8: 16 – bit Ai(ropro(essor

6

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(ontains pins that are both add and data 9&ultiple/ed:

(ontains lat(h de(oder

67, 68, 6 (ontains Pins that (an di.ide reuen(' 9/2" /3:

M!ern M)r!pr!)ess!r 286 - 80286

386 - 80386486 - 80486Pentiu&

Spee ! t*e M)r!pr!)ess!r - &easured in &egahert 9AI: – &illion hert" JI – billion hert

Per!r(an)e ! t*e M)r!pr!)ess!r - di(tated &ainl' b' its nterna$ es/n !r ar)*te)t're" and the

n'(#er ! #ts ! ata it (an pro(ess at an' one ti&e!

1. M)r!pr!)ess!r ar)*te)t're

a. CISC – +o&ple/ nstru(tion 7et +o&puting- &ost (o&&on &i(ropro(essor ar(hite(ture o &i(ro(o&puters!

#. RISC – edu(ed nstru(tion 7et +o&puting- usuall' used in ?K-based (o&puters su(h as high-end ser.ers

and wor;stations!

). Para$$e$ Pr!)essn/- has a &ulti-pro(essing (apabilit'

Intel’s Model of Microprocessors

• Pentiu& or P+s

• +eleron or *udget P+s

• +entrino or laptops

• taniu& or 7er.er +o&puter

• Keon or Iigh-end Wor;stations and 7er.er P+s

American Micro Devices (AMD)’s Model of Microprocessors

• )thlon or P+s

• Duron or *udget P+s• 5urion or laptops

• pteron or 7er.er +o&puter

2! N'(#er ! #ts ! ata

• ntel 8088 9 (an onl' &o.e data in 8-bit (hun;s

• ntel 80286 – (an &o.e data in 16-bit (hun;s

• ntel 80386 and up - (an &o.e data in 32-bit (hun;s

• +urrentl'" )AD and ntel is de.eloping 64-bit &i(ropro(essor

Note: the hi"her data bit$rate transer% the aster the microprocessor

Inte$ D'a$:C!re Te)*n!$!/"

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- designed or ener/":e)en)" per!r(an)e- boosts &ulti-tas;ing power with i&pro.ed peror&an(e or highl'

&ulti-threaded and (al(ulation-intensi.e appli(ations- i&pro.es &ulti &edia appli(ation su(h as intense networ; ga&ing

Inte$ C!re 2 D'! Te)*n!$!/"- design to in(rease the peror&an(e o Dual-+ore te(hnolog' b'

40L! 5he shared (a(he &e&or' is in(reased b' 4A*!

Inte$ ;'a C!re Te)*n!$!/"- an integration o two +ore 2 Duo dual-(ore &i(ropro(essors on a

single substrate

AMD T'r!n 85<2 D'a$ C!re M!#$e Te)*n!$!/"- )AD .ersion o ntel Dual-+ore 5e(hnolog'- deli.ers &ulti-tas;ing peror&an(e or both 32-bit and 64-bit

en.iron&ents!- boost long batter' lie and better s'ste& se(urit' with ,nhan(ed

@irus Prote(tion eature!

MA=OR STRUCTURAL COMPONENTS O- THE CPU

1!: C!ntr!$ Unt – (ontrols the operation o the +P2!: Art*(et) & L!/) Unt 0ALU – peror&s the (o&puters data

pro(essing un(tions3!: Re/sters – pro.ides internal storage to the +P!4!: CPU nter)!nne)t!n – (o&&uni(ation a&ong + and )G!

LOGICAL UNIT PARTITIONS O- THE PROCESSOR

1. E<e)'t!n Unt 0EU- e/e(utes instru(tions and

arith&eti( and logi(al operations!- (ontains an )rith&eti( and

Gogi( nit 9)G:" +ontrol nit 9+:and a

nu&ber o registers! 2. B's Intera)e Unt 0BIU:

- deli.ers instru(tion and data to,!

- &anage the *us +ontrol nit9*+: 7eg&ent

Re/sters an Instr')t!n >'e'e- (ontrols the buses thattranser data to the ," to&e&or' and to e/ternal de.i(es- pro.ide a((ess to instru(tions!

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SEGMENTS & ADDRESSING

Se/(ents- spe(ial areas deined in a progra& or (ontaining the (ode"

the data and what is ;nown as the sta(;!- it begins on a paragraph boundar' or a lo(ation e.enl'

di.isible b' 16 or 10I!

3 Man Se/(ents

&' Code Se"ments (CS)- (ontains the &a(hine instru(tions that are to e/e(ute! 5he +7

register addresses the (ode seg&ent!

*' Data Se"ment (DS )- (ontains a progra&Ms deined data" (onstants and wor; areas! 5he

D7 register addresses the data seg&ent!

+' Stac, Se"ment (SS)- (ontains an' data and addresses that the progra& needs to sa.e

te&poraril' or or use b' 'our own subroutines! 5he 77 registers addressesthe sta(; seg&ent!

Se"ment Oset (Displacement)- distan(e in b'tes ro& the seg&ent address to another lo(ation

within the seg&ent!

Re/ster internal &e&or' o the &i(ropro(essor wherein it a(ts as a

s(rat(h pad or (al(ulations" te&porar' storage or logi( operation!

Se"ment Re"isters-pro.ides or addressing an area o &e&or' ;nown as the (urrent

seg&ent!

1. CS 0C!e Se/(ent holds the starting address o the (ode

seg&ent!2. DS 0Data Se/(ent de(laration" initialiation an'thing regards in

the data!3. SS 0Sta)? Se/(ent reser.ed spa(e or the storage o so&e

inor&ation4. ES 0E<tra Se/(ent use in the string operation the ph'si(al

&e&or' lo(ation o string!

Genera$ P'rp!se Re/ster

the' (an be used as a te&porar' storage o data and has a spe(ial

purpose!1! A))'('$at!r 0A@ holds te&porar' results ater an arith&eti( and

logi( operation2! Base 0B@ oten holds the base 9oset: address o the data lo(ated

in the &e&or' or a &e&or' lo(ation address!3! C!'nt 0C@ (ontains the (ount or (ertain instru(tions!

used or loops" shit and rotate instru(tions!

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4! Data 0D@ data register use to hold data input and output!

also or arith&eti( and logi( operation!

Programmer Visible Architecture • Progra&&er .isible registers<

Ine< an P!nter Re/ster

1. Ine< re/ster a. S!'r)e ne< 0SI used to address sour(e data indire(tl' or

use with the string instru(tions! b. Destnat!n ne< 0DI used to address destination data

indire(tl' or use with the string instru(tion!2. P!nter re/ster

a! SP 0Sta)? p!nter used to address data in a G 9Gast n

irst ut: in the sta(; &e&or'! used in PushPop and +alleturn

instru(tion!b! BP 0Base p!nter use to address an arra' o data on the

sta(; seg&ent!

(! IP 0Instr')t!n p!nter used to address the ne/t instru(tionto be e/e(uted!

-$a/ Re/sterst is also (alled status registers! t indi(ates the status o the

&i(ropro(essor ater arith&eti( operations!

T"pes ! -$a/s

&' Carry -la" (C-)- indi(ate a (arr' after addition or borrow ater subtra(tion! +N0 i there

is no (arr'borrow" otherwise= +N1= t is Oust li;e o.erlow or unsignednu&bers!

+

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*' !arity -la" (!-)- is logi( 0 or odd parit' and logi( 1 or e.en parit'! Parit' is the

nu&ber o 1Ms in the result o arith&eti( operations" only in the L!"# $%&" !'ote If the result of the arithmetic operation is ero* the Parity $it + ,-

+' Auxiliary -la" (A-)- holds a (arr' ater addition or borrow ater subtra(tion between bit

position 3 and 4 o the result!Note: A- . &% i there is carry or borrow between bit + and /'

otherwise% e0uals 1'

/' 2ero -la" (2-)- indi(ates that the result o an arith&eti( or logi( operation is ero!

3' Si"n -la" (S-)- indi(ates arith&eti( sign o the result ater an addition or subtra(tion!'ote ./+ 0 (1)* ./+, (2)

4' 5rap -la" (5-)- when trap is set" it enables trapping through the on-(hip debugging

eature!

6' 7nterrupt -la" (7-)- (ontrol the operation o the intr input pin! N 1 when intr is enabled"

N0 when it is disabled!

8' Direction -la" (D-)- (ontrols the sele(tion o the in(re&entde(re&ent or D or 7!

9' Overlow -la" (O-)- indi(ates that an o.erlow o((ur ater an arith&eti( and logi(al

operations!- N0 i there is no o.erlow= otherwise N1!'ote It is the same 3ith 4arry /lag but for signed numbers-

-LAG BITS POSITION 018 #ts

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

0

O D I T S Z A P C

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