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Bibliographie D. Chanemougame, Conception et fabrication de nouvelles architectures CMOS et étude du transport dans les canaux de conduction ultra minces obtenus avec la technologie SON 212 Bibliographie générale [ABERG 04] I. Aberg, C. Ni Chleirigh, O.O. Olubuyide, X. Duan, J. L. Hoyt High electron and hole mobility enhancements in thin body strain Si/strain SiGe/strain Si heterostructures on insulator, IEDM Tech. Dig., pp. 173-176, 2004 ............................................... 201 [AIME 04] D. Aimé, B. Froment, F. Cacho, V. Carron, S. Descombes, Y. Morand, N. Emonet, F. Wacquant, T. Farjot, S. Jullian, C. Laviron, M. Juhel, R. Pantel, R. Molins, D. Delille, A. Halimaoui, D. Bensahel, and A. Souifi Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS, IEDM Tech. Dig., pp. 87-90, 2004............................................................... 34 [ALIEU 98] J. Alieu, P. Bouillon, R. Gwoziecki, D. Moi, G. Bremond, T. Skotnicki Optimisation of SiGe channel heterostructures for 0.15/0.18μm CMOS Process, Proc. ESSDERC, sept. 1998, Bordeaux, France, p144, 1998............................................................................................ 196 [ANCONA 87] M. G. Ancona, H. F. Tiersten Macroscopic physics of the silicon inversion layer, Physics Rev. B, vol. 35, n°15, 1987 .............. 144 [AVERIN ET LIKHAREV 86] Averin and K. K. Likharev Coulomb Blockade of Tunneling, and Coherent Oscillations in Small Tunnel Junctions, J. Low Temp. Phys., vol. 62, n° 3/4, pp. 345-372, 1986 ................................................................................. 165 [BALESTRA 87] F. Balestra, S. Cristoloveanu et al. Double gate Silicon On Insulator transistor with volume inversion, a new device with greatly enhanced performance, Electron Devices Letter, vol.8, n°9, pp. 410-412, septembre 1987........... 50 [Barraud 01] S. Barraud Effet d’une répartition discrète et aléatoire des impuretés dans le canal des MOSFETs sub- 100nm, Etude théorique par simulation Monte Carlo 3D, thèse de doctorat, Université d’Orsay- Paris Sud, 2001 ....................................................................................................................................... 144 [BIANCHI 02] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance, IEDM Tech. Dig., pp. 117-120, 2002 .............................................................................. 36 [Bœuf 02] F.Boeuf, X. Jehl, M. Sanquer, T. Skotnicki Controlled Single Electron Effects in Nanometric MOSFETs, Proc. of Silicon NanoWorkshop, Honolulu, HI, pp.61-62, 2002 ............................................................................................................... 168 [BŒUF 04] F.Boeuf, F. Payet, N. Casanova, Y. Campidelli, N. Villani, O. Kermarrec, J.M. Hartmann, N. Emonet, F. Leverd, P. Morin, C. Perrot, V. Carron, C. Laviron, F. Arnaud, S. Jullian, D. Bensahel, T. Skotnicki

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Page 1: Conception et fabrication de nouvelles architectures CMOS ...docinsa2.insa-lyon.fr/these/2005/chanemougame/12_biblio_generale.pdf · Double gate Silicon On Insulator transistor with

Bibliographie

D. Chanemougame, Conception et fabrication de nouvelles architectures CMOS et étude du transport dans les canaux de conduction ultra minces obtenus avec la technologie SON

212

Bibliographie générale [ABERG 04] I. Aberg, C. Ni Chleirigh, O.O. Olubuyide, X. Duan, J. L. Hoyt High electron and hole mobility enhancements in thin body strain Si/strain SiGe/strain Si heterostructures on insulator, IEDM Tech. Dig., pp. 173-176, 2004 ............................................... 201 [AIME 04] D. Aimé, B. Froment, F. Cacho, V. Carron, S. Descombes, Y. Morand, N. Emonet, F. Wacquant, T. Farjot, S. Jullian, C. Laviron, M. Juhel, R. Pantel, R. Molins, D. Delille, A. Halimaoui, D. Bensahel, and A. Souifi Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS, IEDM Tech. Dig., pp. 87-90, 2004............................................................... 34 [ALIEU 98] J. Alieu, P. Bouillon, R. Gwoziecki, D. Moi, G. Bremond, T. Skotnicki Optimisation of SiGe channel heterostructures for 0.15/0.18µm CMOS Process, Proc. ESSDERC, sept. 1998, Bordeaux, France, p144, 1998............................................................................................ 196 [ANCONA 87] M. G. Ancona, H. F. Tiersten Macroscopic physics of the silicon inversion layer, Physics Rev. B, vol. 35, n°15, 1987.............. 144 [AVERIN ET LIKHAREV 86] Averin and K. K. Likharev Coulomb Blockade of Tunneling, and Coherent Oscillations in Small Tunnel Junctions, J. Low Temp. Phys., vol. 62, n° 3/4, pp. 345-372, 1986 ................................................................................. 165 [BALESTRA 87] F. Balestra, S. Cristoloveanu et al. Double gate Silicon On Insulator transistor with volume inversion, a new device with greatly enhanced performance, Electron Devices Letter, vol.8, n°9, pp. 410-412, septembre 1987........... 50 [Barraud 01] S. Barraud Effet d’une répartition discrète et aléatoire des impuretés dans le canal des MOSFETs sub-100nm, Etude théorique par simulation Monte Carlo 3D, thèse de doctorat, Université d’Orsay-Paris Sud, 2001 ....................................................................................................................................... 144 [BIANCHI 02] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance, IEDM Tech. Dig., pp. 117-120, 2002 .............................................................................. 36 [Bœuf 02] F.Boeuf, X. Jehl, M. Sanquer, T. Skotnicki Controlled Single Electron Effects in Nanometric MOSFETs, Proc. of Silicon NanoWorkshop, Honolulu, HI, pp.61-62, 2002 ............................................................................................................... 168 [BŒUF 04] F.Boeuf, F. Payet, N. Casanova, Y. Campidelli, N. Villani, O. Kermarrec, J.M. Hartmann, N. Emonet, F. Leverd, P. Morin, C. Perrot, V. Carron, C. Laviron, F. Arnaud, S. Jullian, D. Bensahel, T. Skotnicki

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Strained-Si for CMOS 65nm node, Si0.8Ge0.2 SRB or Low Cost approach ?, SSDM, pp. 16-17, 2004...........................................................................................................................................................130 [BŒUF 05b] F. Boeuf, S. Monfray, A. Pouydebasque, M. Müller, F.Payet, C. Ortolland and T. Skotnicki 45nm Conventional Bulk and Bulk+ Architectures for Low-Cost GP/LP Applications, SSDM, p28, 2005 ..................................................................................................................................................132 [BOREL 04] S.Borel et al. Control of the selectivity between SiGe and Si in isotropic etching processes, Japanese Journal of Applied Physics, vol 43 (6B), pp 3964-3966, 2004 ................................................................................61 [Bouillon 97] P. Bouillon Etude et application de nouvelles architectures du canal aux dispositifs MOS avancés, thèse de doctorat, INPG, 1997 ................................................................................................................................31 [BRUEL 95] M.Bruel et al. Silicon On Insulator material technology, Electronics Letters, vol 31, n°14, pp 1201-1202, 1995..39 [BYUN 90] Y. H. Byun, K. Lee, M Shur Unified charge control model and subthreshold current in heterostructure field-effect transistors, IEEE Electron Devices Letters, vol. 11, n°1, p50-53, 1990 .............................................102 [CERUTTI 05a] R. Cerutti et al. New design adapted planar double gate process for performant low nanoelectronics stand by power application Silicon Nano Workshop, Kyoto, Japan, 2005........................................................................................50 [CERUTTI 05b] R. Cerutti Communications internes orales, STMicroelectronics, Crolles, 2005................................................50 [CERUTTI 06] R. Cerutti Transistor à grilles multiples adapté à la conception, thèse de doctorat, INPG, 2006..................174 [CHAIN 97] K. Chain, J. Huang, J. Duster, P. Ko, C. Hu A MOSFET electron mobility model of wide temperature range (77–400 K) for IC simulation, Semicond. Sci. Technol., vol. 12, p355–358, 1997 .......................................................110, 111, 113, 114 [CHAN 03] V. Chan et al. High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporation strain engineering, IEDM Tech. Dig. p77 2003..........................................................190 [CHEN 04] Ch. Chen et al. Stress Memorization Technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application, Proc. Symp. VLSI Tech., 2004...........................36

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[DORIS 02] B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, F. Jamin, L. Shi, W. Natzle, H. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J. Miller, H. P. Wong, and W. Haensch Extreme scaling with ultra-thin Si channel MOSFETs, IEDM Tech. Dig., pp. 267 - 270, December 2002 ............................................................................................................................................................ 51 [DORIS 05] B. Doris, Y.H. Kim†, B. P. Linder†, M. Steen†, V. Narayanan†, D. Boyd†, J. Rubino†, L. Chang†, J. Sleight, A. Topol†, E. Sikorski, L. Shi, K. Wong, K. Babich†, Y. Zhang†, M. Ieong High Performance FDSOI CMOS Technology with Metal Gate and High-k, Proc. VLSI Tech., p214, 2005................................................................................................................................................ 133 [DUBOIS 01] E. Dubois, G. Larrieu Advanced Source/Drain architecture using very low Schottky barriers device design and material engineering, ESSDERC, Nuremberg, Germany, sept. 14, 2001, pp. 203 - 206, 2001 ....... 49 [DUMONT 05] B. Dumont, A. Pouydebasque, F. Lallement, D. Lenoble, G. Ribes, J. M. Roux, S. Vanbergue, T. Skotnicki PLAsma Doping for S/D Extensions: Device Integration, Gate Oxide Reliability and Circuit Demonstration, Proc. ESSDERC, Grenoble, France, 12-16 sept. 2005, pp. 113-116, 2005 .............. 32 [EL-FAHRANE 04] R. El-Fahrane Contribution à l’étude et à l’intégration en technologie CMOS avancée de jonctions ultra minces formées par des procédés à faible budget thermique, thèse de doctorat, Université Paul Sabatier Toulouse, 2004.......................................................................................................................................... 33 [EN 01] W.G. En, Ju Dong-Hyuk; Darin Chan, S. Chan, O. Karlsson Reduction of STI/active stress on 0.18 µm SOI devices through modification of STI process, IEEE Int. SOI Conf., pp. 85-86, 2001 .................................................................................................... 190 [Fenouillet-Beranger 01] C. Fenouillet-Beranger Etude physique de dispositifs SOI partiellement désertés fortement sub-microniques, thèse de doctorat, INPG, 2001 ............................................................................................................................... 37 [Fenouillet-Beranger 03] C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, F. Boeuf Requirements for ultra-thin-film devices and new materials on CMOS roadmap, Int. SOI Conf., pp. 145-146, 2003...................................................................................................................................... 43 [FERRY 84] D. K. Ferry Effects of surface roughness in inversion layer transport, IEDM Tech. Dig., p605–8, 1984........ 112 [FIS 96] 19M. V. Fischetti and S. E. Laux Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys, J. Applied Phys., vol. 80, p2234, 1996.................................................................................................. 200

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[FISCHETTI 02] M. V. Fischetti, F. Ga´miz, W. Hansch On the enhanced electron mobility in strained-silicon inversion layers, J. Applied Phys., vol. 92, p7320, 2002 ..............................................................................................................................................134 [FISCHETTI 03] M.V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, K. Rim Six-band k p calculation of the hole mobility in silicon inversion layers - Dependence on surface orientation, strain, and silicon thickness, J. Applied Phys., vol. 94, p1079–1095, 2003………….. .............................................................................................................98, 112, 117, 120, 121, 122, 126, 191 [FISCHETTI 93] M. V. Fischetti, S. E. Laux Monte Carlo study of electron low field mobility inversion layer, Phys. Rev. B, vol. 48, 2244, 1993...........................................................................................................................................................102 [FISCHETTI 96] 19M. V. Fischetti and S. E. Laux Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys, J. Applied Phys., vol. 80, p2234, 1996 ..........................................................................................126, 191 [FISCHETTI 96] M. V. Fischetti and S. E. Laux Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys, J. Applied Phys., vol. 80, p2234, 1996 ..................................................................................................126 [FOSSUM 03] J. G. Fossum Performance Projections of Scaled CMOS Devices and Circuits With Strained Si-on-SiGe Channels, Trans. Electron Devices, p 1042, 2003........................................................................133, 136 [FUCHS 05] E. Fuchs, P. Dollfus, G. Le Carval, S. Barraud, D. Villanueva, F. Salvetti, H. Jaouen, T. Skotnicki A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET, Trans. Electron Devices, vol. 52, n°10, pp2280-2289, October 2005...............................136 [FULTON ET DOLAN 87] T. A. Fulton et G. J. Dolan Observation of single-electron charging effects in small tunnel junctions, Physical Review Letters, vol. 59, pp. 109-112, 1987 .........................................................................................................165 [GALLON 03] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Blanchi, R. Gwoziecki, C. Raynaud Electrical Analysis of Mechanical Stress Induced by Shallow Trench Isolation, Proc. ESSDERC, Estoril, Portugal, 16-18 septembre 2003, p 359, 2003 .........................................................................190 [GALLON 04] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, H. Dansas Electrical Measurement of Mechanical Stress Induced by STI using Externally Applied Stress, Trans. Electron Devices, vol 51, number 8, august 2004 .....................................................................36

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[GALLON 05] C. Gallon C. Gallon, C. Fenouillet-Beranger, S. Denorme, F. Boeuf, V. Fiori, N. Loubet, T. Kormann, M. Broekaart, P. Gouraud, F. Leverd, G. Imbert, C. Chaton, C. Laviron, L. Gabette, F. Vigilant, P. Garnier, H. Bernard, A. Tarnowka, A. Vandooren, R. Pantel, F. Pionnier, S. Jullian, S. Cristoloveanu, T. Skotnicki Effect of Process Induced Strain in 35 nm FDSOI Devices with Ultra-Thin Silicon Channels, SSDM, Kobe, Japan, september 12-15 2005, p34, 2005...................................................................... 132 [GAMIZ 99] F. Gamiz, J. B. Roldan, J. A. Lopez-Villanueva, P-Cartujo-Cassinello, J. E. Carceller Surface roughness at the Si–SiO2 interfaces in fully depleted silicon-on-insulator inversion layers, J. Applied Phys., vol. 86, 6854, 1999 ....................................................................................... 123 [GHANI 03] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors, IEDM Tech. Dig., pp. 978-980, 2003 ......................................... 36 [GOO 03] Jung-Suk Goo, Qi Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, Ming-Ren Lin Band offset induced threshold variation in strained-Si nMOSFETs, Electron Device Letters, vol. 24, n°9, pp. 568-570, 2003 .................................................................................................................... 133 [GOTO 04] K Goto, S. Satoh, H. Ohta, S. Fukuta, T. Yamamoto, T. Mori, Y. Tagawa, T. Sakuma, T. Saiki, Y. Shimamune, A. Katakami, A. Hatada, H. Morioka, Y. Hayami, S. Inagaki, K. Kawamura, Y. Kim, H. Kokura, N. Tamura, T. Sugii, K. Hashimoto Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs, IEDM Tech. Dig., pp. 209-212, 2004 ...................................................................................................... 36 [HAOND 91] M.Haond, O.Le Néel SOI CMOS devices, INFOS proceedings, 1991.................................................................................... 39 [HARRISON 03] S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Jullian, R. Pantel, S. Descombes, D. Dutartre, Y. Morand, M. P. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteanu, J. Autran, and T. Skotnicki Highly performant double gate MOSFET realized with SON process, IEDM Tech. Dig., pp. 449 - 452, December 2003 ................................................................................................................................. 50 [HARRISON 05] S. Harrison Dispositifs GAA en technologie SON, conception, caractérisation et modélisation en vue de l’intégration dans les noeuds CMOS avancés, thèse de doctorat, Université de Provence 2005........................................................................................................................................ ..34, 50, 52, 88, 174

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[HARTMAN 03] M. Von Hartman, A.-C. Lindgren, P. E. Hellstrom, M. Ostling, T. Ernst, L. Brevard, S. Deleonibus Influence of gate width on 50 nm gate length Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs, Proc. ESSDERC, Estoril, Portugal, pp. 529-532, 2003 ..................................................................................196 [HOBBS 03] C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H. Tseng, B. White, P. Tobin Fermi level pinning at the polySi/metal oxide interface, Proc. Symp. VLSI Tech., pp. 9-10, 2003......................................................................................................................................................................35 [IONESCU 02] A. M. Ionescu, M.J. Declercq, S. Mahapatra, K. Banerjee, and J. Gautier Few Electron Devices, Towards Hybrid CMOS-SET Integrated Circuits, Proceedings of the 39th Design Automation Conference, New Orléans, LA, pp. 88-93, 2002 ..............................................171 [ITRS 03] European Semiconductor Industry Association International Technology Roadmap For Semiconductors, Edition 2003. Austin, Tex. : ITRS, p. 646...................................................................................................................................................25, 29, 49 [JOEN 89] D. S. Joen, D. E. Burk MOSFET electron inversion layer mobilities—a physically based semi-empirical model for a wide temperature range, IEEE Trans. Electron Devices, vol. 36, p1456–63, 1989 .........................112 [JOSSE 00] E. Josse Nouvelles architectures de grille pour les générations CMOS 0.1µm et en deça, thèse de doctorat, INPG, 2000 ..........................................................................................................................28, 33 [JURCZAK 99a] M. Jurczak, T. Skotnicki, G. Ricci, Y. Campidelli, C. Hernandez, D. Bensahel Study on Enhanced performance in NMOSFETs on strained silicon, Proc. ESSDERC, Leuven, Belgium, sept. 1999, pp. 304-307, 1999...................................................................................................35 [JURCZAK 99b] M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J.-L. Regolini, C. Morin, A. Schiltz, J. Martins, R. Pantel, J. Galvier SON (Silicon On Nothing) – a new device architecture for the ULSI Era, Proc. Symp. VLSI Tech., pp. 29-30, 1999...........................................................................................................................................37 [KOGA 2002] J. Koga, S. Takagi, A. Toriumi Influences of Buried-Oxide Interface on Inversion-Layer Mobility in Ultra-Thin SOI MOSFETs, Trans. Electron Devices, vol. 49, n° 6, june 2002 ................................................................................123 [KOOMEN 73] J. Koomen Investigation of the MOST channel conductor in weak inversion, Solid State Electronics, 16, 801 1973...........................................................................................................................................................197

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[KRIVOKAPIC 03] Z. Krivokapic, W. Maszara, F. Arasnia, E Paton, Y. Kim, L. Washington, E. Zhao, J. Chan, J. Zhang, A. Marathe, M-R. Lin High Performance 25nm FDSOI Devices with Extremely Thin Silicon Channel, Proc. VLSI Tech., 2003 .......................................................................................................................................................... 133 [LALLEMENT 05] F. Lallement Etude, réalisation et intégration de procédés industriels de dopage des semiconducteurs par Plasma. Application à la technologie CMOS 65 nm sur plaques de 300 mm de diamètre, thèse de doctorat, INPG 2005 ................................................................................................................................ 32 [LEE 91] K. Lee, J. Choi, S. Sim, C. Kim Physical understanding of low field carrier mobility in Si mosfets inversion layer, IEEE Trans. Electron Devices, vol. 38, n°8, août 1991 ............................................................................ 102, 103, 104 [LIME 03] F. Lime, C. Guiducci, R. Clerc, G. Ghibaudo, C. Leroux, T. Ernst Characterization of effective mobility by split C(V) technique in N-MOSFETs with ultra thin gate oxides, Solid State Electron., vol. 47, pp. 1147–1153, 2003....................................................... 197 [LUNDSTROM 02] M. Lundstrom, Z. Ren Essential Physics of Carrier Transport in Nanoscale MOSFETs, Trans. Electron Devices, vol. 49, n°1, p133, 2002................................................................................................................................ 137, 199 [MATHIEU 98] H. Mathieu Physique des semiconducteurs et des composants électroniques, Paris : édition Masson, 1998 97, 99 [MIZUNO 04] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda, S. Takagi High velocity electron injection MOSFETs for ballistic transistors using SiGe/strained-Si heterojunction source structures, Proc. Symp. VLSI Tech., pp. 202-203, 2004 .............................. 201 [MIZUNO 99] T Mizuno, S Takagi, N Sugiyama, J Koga, T Tezuka, K Usuda, T Hatakeyama, A Kurobe, A Toriumi High performance strained Si p MOSFETs on SiGe on insulator substrates fabricated by SIMOX technology, IEDM Tech. Dig., pp. 934–937, 1999 ................................................................................ 35 [MONFRAY 01] S.Monfray et al. First 80nm SON (Silicon On Nothing) MOSFETs with perfect morphology and high electrical performance, IEDM Tech. Dig., 2001 .................................................................................................... 40 [MONFRAY 01] S. Monfray, C.Julien, P.Ribot, F.Boeuf, D.Dutartre, J.Martins, E.Sondergard and T. Skotnicki Optimized Si/SiGe notched gates for CMOS, Proc. of ESSDERC, Nuremberg, Germany, 11-13 september, 2001...................................................................................................................................... 168

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