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LLectureecture 8:8:Test Test benchesbenches & & AttributesAttributes
Plan
• Test benches
• Attributes
Test benches
Testbench - basics
• A testbench is a program that mimics a physical lab bench
• Testbenches have become the standard method to verify HLL (High-Level Language) designs
• There are two main methods of preparingtestbenches:– By the use of a graphical interface
– By writing a simulation code
Testbench - basics• Typically, testbenches perform the following tasks:
– Instantiate the design under test (DUT)
– Stimulate the DUT by applying test vectors to the model
– Output results to a terminal or waveform window for visual inspection
– Optionally compare actual results to expected results
• Typically, testbenches are written in the industry-standard VHDL or Verilog hardware description languages.
• Testbenches invoke the functional design, then stimulate it
Testbench Verification Flow
Testbench Waveform Editor
Testbench VHDL code
Simulation results
Testbench construction
Testbench - construction
• Typically testbenches written in VHDL containsections:– Entity and Architecture Declaration
– Signal Declaration
– Instantiation of Top-level Design
– Provide Stimulus
Testbench - construction• Generating clock signal:
Constant ClockPeriod : TIME := 10 ns;
-- Clock Generation method 1:
Clock
Testbench - construction• Providing Stimulus (absolute time):
Testbench - construction• Providing Stimulus (relative time):
Testbench - construction• Things to remember:
– initial blocks are executed concurrently along with
other process and initial blocks in the file
– within each (process or initial) block, events are
scheduled sequentially, in the order written
– stimulus sequences begin in each concurrent block at
simulation time zero
– Multiple blocks should be used to break up complex
stimulus sequences into more readable and
maintainable code
Testbench - construction
• Displaying results:– Facilitated in Verilog – dedicated keywords
– In VHDL std_textio package functions should be used
Testbench - construction• Self-checking testbench:
– Self-checking testbenches are implemented by
placing a series of expected vectors in a testbench
file
– Vectors are compared at defined run-time intervals
to actual simulation results
– If actual results match expected results, the
simulation succeeds
– In VHDL vectors are read from a file (std_textio)
Testbench - construction
Testbench – example (counter)
Testbench – example (testbench 1/2)
Testbench – example (testbench 2/2)
Testbench – reading from a file• Reading from files is very important for VHDL
simulation
• An example entity header:
• Data is read from a file sim.dat at every rising clock edge and applied to the output vector Y
• Once every line of the file is read the EOG (End Of Generation) flag is set
Testbench – reading from a file• The main part of the architecture body:
ISE Simulator (ISim)
ISim - features• ISim is integrated HDL simulator used to
simulate Xilinx FPGA and CPLD designs
• ISE Simulator can be used to simulate both RTL and gate-level designs.
• ISim in Webpack ISE has Performance Derationwhen exceeding 50,000 lines of HDL code (3x-10x slower)
• The line count includes both testbench and source code lines. The Xilinx libraries are not included in the line count.
ISim – launching behavioral simulation
• Simulation is launched from ISE Process Pane
ISim – launching behavioral simulation
• Right-click on „Simulate Behavioral Model” gives(Simulation Run Time is important!):
ISim – launching behavioral simulation
• Double click on „Simulate Behavioral Model”starts ISim:
ISim – graphical environment
• The Instances and Processes panel displays the
block (instance and process) hierarchy
associated with the wave configuration open in
the Wave window.
• Instantiated and elaborated entities/modules
are displayed in a tree structure, with entity
components being ports, signals and other
entities/modules.
ISim – graphical environment
• The Source Files panel displays the list of all the
files associated with the design.
• The list of files is provided by the fuse command
during design parsing and elaboration, which is
run in the background for GUI users.
• The HDL source files are available for quick
access to the source code
ISim – graphical environment
• The Objects panel displays all ports and signals
associated with the selected instances and
processes in the Instances and Processes panel.
• At the top of the panel, the Simulation Objects
displays which instance/process is selected in
the Instances and Processes panel whose objects
and their values are listed in the Objects panel.
ISim – graphical environment
• The Wave window displays signals, buses and
their waveforms.
• Each tab in the Wave window represents a wave
configuration, which consists of a list of signals
and buses, their properties, and any added wave
objects, such as dividers, cursors, and markers.
ISim – examining the design
• Several steps to analyze the functional behavior
of the simulated design:
– Running and restarting the simulation to review the
design functionality,
– Adding signals from the test bench and other design
units to the wave window
– Adding groups in order to better identify signals in
the wave window
ISim – examining the design
• Several steps to analyze the functional behavior
of the simulated design:
– Changing signal and wave window properties to
better interpret and review the signals in the wave
window.
– Using markers and cursors to highlight key events in
the simulation and to perform zoom and time
measurement features.
Attributes
Attributes
• Attributes are a feature of VHDL that allow to extract additional information about an object (such as a signal, variable or type) that may not be directly related to the value that the object carries.
• Attributes also allow to assign additional information (such as data related to synthesis) to objects in your design description.
Attributes
• There are two classes of attributes: – predefined as a part of the 1076 standard,
– introduced outside of the standard:• by the designer
• by the design tool supplier (like Xilinx or Altera)
Predefined attributes
• There are five kinds of predefined attributes:– Returning value
– Returning function
– Returning signal
– Returning type
– Returning range
Value kind attributes
• ‘Left — Returns the left-most element index (the
bound) of a given type or subtype.
– Example: type bit_array is array (1 to 5) of bit;
– variable L: integer := bit_array’left; -- L has a value of 1
• ‘Right — Returns the right-most element index
(the bound) of a given type or subtype.
Value kind attributes
• ‘High — returns the upper bound of a given
scalar type or subtype
– Example: type bit_array is array(-15 to +15) of bit;
– variable H: integer := bit_array’high; -- H has a value of 15
• ‘Low — returns the lower bound of a given scalar
type or subtype
Value kind attributes
• ‘Length - returns the length (number of elements)
of an array.
– Example: type bit_array is array (0 to 31) of bit;
– variable LEN: integer := bit_array’length -- LEN has a value of 32
Value kind attributes
• ‘Ascending—(VHDL ’93 attribute) returns a
boolean true value of the type or subtype is
declared with an ascending range
– Example: type asc_array is array (0 to 31) of bit;
– type desc_array is array (36 downto 4) of bit;
– variable A1: boolean := asc_array’ascending; -- A1 has a value
of true
– variable A2: boolean := desc_array’ascending; -- A2 has a
value of false
Value kind attributes
• ‘Structure—returns a true value if the prefix
(which must be an architecture name) includes
references to lower-level components (false
otherwise)
• ‘Behavior—returns a true value if the prefix
(which must be an architecture name) does not
include references to lower-level components.
Value kind attributes
• ‘Simple_name—returns a string value corresponding to
the prefix, which must be a named entity
• ‘Instance_name—returns a string value corresponding to
the complete path (from the design hierarchy root) to the
named entity specified in the prefix, including the names
of all instantiated design entities.
• ‘Path_name—returns a string value corresponding to the
complete path (from the design hierarchy root) to the
named entity specified in the prefix.
Function kind attributes
• ‘Pos(value)—returns the position number of a
type value.
– Example: type state_type is (Init, Hold, Strobe, Read, Idle);
– variable P: integer := state_type’pos(Read); -- P has the value
of 3
• ‘Val(value)—returns the value corresponding to a
position number of a type value.
– Example: type state_type is (Init, Hold, Strobe, Read, Idle);
– variable V: state_type := state_type’val(2); -- V has the value
of Strobe
Function kind attributes
• ‘Succ(value)—returns the value corresponding to
position number after a given type value.
– Example: type state_type is (Init, Hold, Strobe, Read, Idle);
– variable V: state_type := state_type’succ(Init); -- V has the
value of Hold
• ‘Pred(value)—returns the value corresponding to
position number preceding a given type value.
– Example: type state_type is (Init, Hold, Strobe, Read, Idle);
– variable V: state_type := state_type’pred(Hold); -- V has the
value of Init
Function kind attributes
• ‘Leftof(value)—returns the value corresponding to
position number to the left of a given type value.
– Example: type state_type is (Init, Hold, Strobe, Read, Idle);
– variable V: state_type := state_type’leftof(Idle); -- V has the
value of Read
• ‘Rightof(value)—returns the value corresponding
to position number to the right of a given type
value.
– Example: type state_type is (Init, Hold, Strobe, Read, Idle);
– variable V: state_type := state_type’rightof(Read); -- V has the
value of Idle
Function kind attributes
• ‘Left(value)—returns the index value
corresponding to the left bound of a given array
range.
– Example: type bit_array is array (15 downto 0) of bit;
– variable I: integer := bit_array’left(bit_array’range); -- I has
the value of 15
• ‘Right(value)—returns the index value
corresponding to the right bound of a given array
range.
Function kind attributes
• ‘High(value)—returns the index value
corresponding to the upper-most bound of a given
array range.
– Example: type bit_array is array (15 downto 0) of bit;
– variable I: integer := bit_array’high(bit_array’range); -- I has
the value of 15
• ‘Low(value)—returns the index value
corresponding to the lower bound of a given array
range.
Function kind attributes• ‘Event—returns a true value of the signal had an event
(changed its value) in the current simulation cycle.Example: process(Rst,Clk)
begin
if Rst = ‘1’ then
Q
Function kind attributes• ‘Active—returns true if any transaction (scheduled event)
occurred on this signal in the current simulation cycle
Example: process
variable A,E: boolean;
begin
Q
Function kind attributes• ‘Last_event—returns the time elapsed since the previous
event occurring on this signal.Example: process
variable T: time;
begin
Q
Function kind attributes• ‘Last_value—returns the value of the signal prior to the
last event.Example: process
variable V: bit;
begin
Q
Function kind attributes• ‘Last_active—returns the time elapsed since the last
transaction (scheduled event) of the signal.Example: process
variable T: time;
begin
Q
Function kind attributes• ‘Value(string)—(VHDL ’93 attribute) returns a value, of a
type specified by the prefix, corresponding to the
parameter string.
Example: write(a_outbuf,string’("Enter duration (example:
15)"));
writeline(OUTPUT,a_outbuf);
readline(INPUT,a_inbuf);
read(a_inbuf,induration); -- induration is a string type
duration
Signal kind attributes• ‘Delayed(time)—creates a delayed signal that is identical
in waveform to the signal the attribute is applied to. (The
time parameter is optional, and may be omitted.)Example: process(Clk’delayed(hold))
-- Hold time check for input Data
begin
if Clk = ‘1’ and Clk’stable(hold) then
assert(Data’stable(hold))
report "Data input failed hold time check!"
severity warning;
end if;
end process;
Signal kind attributes• ‘Stable (time)—creates a signal of type boolean that
becomes true when the signal is stable (has no event) for
some given period of time.Example: process
variable A: Boolean;
begin
wait for 30 ns;
Q
Type kind attributes• ‘Base—returns the base type for a given type or subtype.
Example: type mlv7 is (‘0’,’1',’X’,’Z’,’H’,’L’,’W’);
subtype mlv4 is mlv7 range ‘0’ to ‘Z’;
variable V1: mlv4 := mlv4’right;
-- V1 has the value of ‘Z’
variable V2: mlv7 := mlv4’base’right;
-- V2 has the value of ‘W’
variable I1: integer := mlv4’width;
-- I1 has the value of 4
variable I2: integer := mlv4’base’width;
-- I2 has the value of 7
Range kind attributes• ‘Range—returns the range value for a constrained array.
Example: function parity(D: std_logic_vector) return
std_logic is
variable result: std_logic := ‘0’;
begin
for i in D’range loop
result := result xor D(i);
end loop;
return result;
end parity;
Custom Xilinx attributes
• Custom attributes have to be declared:
– In the entity – visibility also in the architecture body
– In the architecture body
• Declaration:
– attribute ram_style: string;
• Usage:
– attribute ram_style of RAM: signal is
"pipe_distributed";
Custom Xilinx attributes
• Attributes vs Constraints:
– Names can be used interchangably for custom
attributes
– We can define subcategories:
• Attributes - property associated with a device architecture
primitive component that generally affects an instantiated
component’s functionality or implementation
• Synthesis constraints - direct the synthesis tool optimization
technique for a particular design or piece of HDL code
• Implementation constraints - instructions given to the FPGA
implementation tools to direct the mapping, placement,
timing, etc. for the implementation tools
Spartan 3E attributes (some☺)
• DLL attributes:
Spartan 3E attributes (some☺)
• Block RAM attributes:
CPLD attributes
FPGA constraints• FPGA constraints can ge split into:
– Grouping Constraints
– Logical Constraints
– Physical Constraints
– Mapping Directives
– Placement Constraints
– Routing Directives
– Synthesis Constraints
– Timing Constraints
– Configuration Constraints
Attributes – to be continued8
Thank you for your attention
References[1] „Combinational Circuits”, http://www.cs.Princeton.EDU/~cos126
[2] http://www.cs.umbc.edu/portal/help/VHDL/
[3] http://ece.wpi.edu/~rjduck/Xilinx%20VHDL%20Test%20Bench%20Tutorial_2.0.pdf
[4] http://www.seas.upenn.edu/~ese171/vhdl/VHDLTestbench.pdf
[5] http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
[6] http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx%20ISE%20Simulator%20(ISim)%20VHDL%20Test%20Bench%20Tutorial.pdf
[7] http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug682.pdf