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Internal note A. Dorokhov, IPHC, Strasbourg, France

CE_18_1 (xFab xh018)

Andrei Dorokhov Institut Pluridisciplinaire Hubert Curien (IPHC)

Strasbourg, France

Internal note, 1/03/2010 

e-mail address: Andrei.Dorokhov@IReS.in2p3.fr

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Internal note A. Dorokhov, IPHC, Strasbourg, France

CE_18_1 layout, 5

melal layers

OUT1

OUT2 OUT3

OUT4

3300 um X 3180 um=10.494 mm^2

64 64

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Internal note A. Dorokhov, IPHC, Strasbourg, France

CE_18_1 description

1. Chip has 4 quarters, each has one analog output, 64 columns and 64 rows (== 1 readout frame == 4096 pixels)

2. Each quarter has 4 sub-matrixes: 64 columns by 16 rows

3. power supply: vddor =+3.3V, vdd, vdda =+1.8V, bias currents for column and source follower

4. Clock, Start, GReset are digital 3.3V inputs 5. Each sub-matrix has separate bias for

collection diodes and common bias (for one quarter) for the additional metal electrode

6. In total up to 16 different pixel designs can be implemented

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Internal note A. Dorokhov, IPHC, Strasbourg, France

CE_18_1 readout modes1. Global reset continuously active (+3.3V): all

pixels (including reset pixels) are put in self-biased mode. Start pulse set address position to (0,0), the output multiplexed to columns with Clock, raw by raw. Counter is circular, so after 4096 it is not necessary to Start again.

2. Global reset not active (0V): the reset for pixels active only first frame (4096 Clocks) after Start, each row (except the first which is always in reset state) is reset and readout immediately after, this gives calibration reference. For the subsequent frames reset is not active, so one can make CDS between current readout (s) and reference.

3. One can pulse Global reset to 3.3V during first 4096 clocks (defined by the start signal), and then readout pixels in subsequent frames.

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Internal note A. Dorokhov, IPHC, Strasbourg, France

CE_18_1 pixel designs

design# Nwell (um) Diffusion(um) PWexclusion RadTol readout status1 2.5x2.5 max possible no SB done2 3.8x3.8 max possible no SB done3 0.45x0.45 max possible no RST done4 3.8x3.8 max possible no RST done5 2.5x2.5 no no SB done6 3.8x3.8 no no SB done7 0.54x0.54 max possible yes RST done8 3.8x3.8 max possible yes RST done9 2x2 no yes(*1) RST done, but..

10 2x2 max possible yes(*1) RST done, but..11 3.8x3.8 no yes(*1) RST (or SB) done, but..12 3.8x3.8 max possible yes(*1) RST (or SB) done, but..13 #1+ampl schema done14 #3+ampl schema done15 #4+ampl+sh schema done16 #3+ampls schema done

(*1) - >> RadTol design errors[1] B1DF : DIFF without NIMP or PIMP is not allowed (except qnva, nedia)[1] B2DF : DIFF crossing NTYPE_WELL or PTYPE_WELL edge is not allowed[1] B3DF : DIFF crossing NWELL edge is not allowed[1] B2GA : Illegal GATE construct