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CHAPTER 1

GATE-LEVEL COMBINATIONAL CIRCUIT

1.1 INTRODUCTIONVHDL stands for VHSIC (very high-speed integrated circuit) hardware description lan-guage. It was originally sponsored by the U.S. Department of Defense and later transferredto the IEEE (Institute of Electrical and Electronics Engineers). The language is formally de-fined by IEEE Standard 1076. The standard was ratified in 1987 (referred to as VHDL 87),and revised several times. This book mainly follows the revision in 1993 (referred to asVHDL 93).

VHDL is intended for describing and modeling a digital system at various levels andis an extremely complex language. The focus of this book is on hardware design ratherthan the language. Instead of covering every aspect of VHDL, we introduce the key VHDLsynthesis constructs by examining a collection of examples. Detailed VHDL coverage maybe explored through the sources listed in the Bibliography.

In this chapter, we use a simple comparator to illustrate the skeleton of a VHDL pro-gram. The description uses only logical operators and represents a gate-level combinationalcircuit, which is composed of simple logic gates. In Chapter 3, we cover the more sophis-ticated VHDL operators and constructs and examine module-level combinational circuits,which are composed of intermediate-sized components, such as adders, comparators, andmultiplexers.

FPGA Prototyping by VHDL Examples. By Pong P.ChuCopyright @ 2008 John Wiley & Sons, Inc. 1

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GENERAL DESCRIPTION 3An identiJier is the name of an object and is composed of 26 letters, digits, and theunderscore (-), as in i0, l , and da ta -b us l- en abl e. The identifier must start with a letter.The comments start with -- and the text after it is ignored. In this book, the VHDL

keywords are shown in boldface type, as in entity, and the comments are shown in italicstype, as in__ t h i s is a c o m m e n t

1.2.2 Library and packageThe first two lines,

l i b r a r y ieee;u s e ieee. td-logic-1164, a l l ;invoke the std- lo gi c- 11 64 package from the i e e e library. The package and library allowus to add additional types, operators, functions, etc. to VHDL. The two statements areneeded because a special data type is used in the code.1.2.3 Entity declarationThe entity declaration

e n t i t y eql i sport (

i0, i l : i n std-logic;e q : o u t std-logic

) ;e n d e q l ;essentially outlines the I/O signals of the circuit. The first line indicates that the name ofthe circuit is e q l , and the port section specifies the I/O signals. The basic format for an I/Oport declaration is

signal-namel, signal-name2, . . . : mode data-type;The mode term can be in or out, which indicates that the corresponding signals flow intoor out of of the circuit. It can also be inout, for bidirectional signals.1.2.4 Data type and operatorsVHDL is a strongly typed language , which means that an object must have a data type andonly the defined values and operations can be applied to the object. Although VHDL is richin data types, our discussion is limited to a small set of predefined types that are suitablefor synthesis, mainly the s td- logic type and its variants.std-logic type The s t d - l o g i c type is defined in the s td -l og ic -I 16 4 package andconsists of nine values. Three of the values, 0 , I and Z ,which stand for logical 0,logical 1, and high impedance, can be synthesized. Two values, U nd X which standfor uninitialized and unknown (e.g., when signals with 0 and 1 values are tiedtogether), may be encountered in simulation. The other four values, - H L and , are not used in this book.

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GENERAL DESCRIPTION 5

(not i0) and (not i l )PO o r p l

Figure 1.1 Graphical representation of a comparator program.

Th e graphical representation of this program is shown in Figure 1.1. The three circuitparts represent the three concu rrent statements. Th e connections am ong these parts areimplicitly specified by the signal and port names. The order of the concurrent statementsis clearly irrelevant and the statements can be rearranged arbitrarily.

1.2.6 Code of a 2-bit comparatorWe can expand the comparator to 2-bit inputs. Let the input be a and b and the outpu t beaeqb. The aeqb signal is asserted w hen bo th bits of a and b are equal. Th e code is shownin Listing 1.2.

Listing 1.2 Gate-level implementation of a 2-bit comparatorl i b r a r y i e e e ;u s e i e e e . s t d - l o g i c - 1 1 6 4 . a l l ;e n t i t y e q 2 i s

p o r t (a , b : i n s t d - l o g i c - v e c t o r ( 1 d o w n t o 0 ) ;a e q b : o u t s t d - l o g i c

) ;e n d e q 2 ;1 0 a r c h i t e c t u r e s o p - a r c h o f e q 2 i ss i g n a l p O , p l , p 2 , p 3 : s t d - l o g i c ;

-- sum of p r o d u c t t e r m sa e q b

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6 GATE-LEVEL COMBINATIONALCIRCUIT

Figure 1.2 Construction of a 2-bit comparator from 1-bit comparators.

1.3 STRUCTURAL DESCRIPTIONA digital system is frequently composed of several smaller subsystems. This allows us tobuild a large system from simpler or predesigned components. VHDL provides a mech a-nism, known as component instantiation, to perform this task. This type of cod e is calledstructural desc ription.An alternative to the design of the 2-bit comparator of Section 1.2.6 is to utilize thepreviously constructed 1-bit com parat ors as the building blocks. Th e diagram is shown inFigure 1.2, in which two 1-bit comparators are used to check the two individual bits andtheir results are fed to an and cell. Th e aeqb signal is asserted only w hen the tw o bits areequal.

Th e correspo ndin g cod e is shown in Listing 1.3. Note that the entity declaration is thesam e and thus is not included.Listing 1.3 Structural description of a 2-bit comparator

a r c h i t e c t u r e struc-arch of eq2 i sb e g i n

s i g n a l e O , e l : s t d - l o g i c ;_- i n s t a n t i a t e t w o 1 - b i t c o m p a r a t o r s

5 eq-bit0-unit : e n t i t y w o r k . ql (sop-arch)eq-bitl-unit : e n t i t y w o r k . ql (sop-arch)-- a a nd b a r e e q u a l i f i n d i v i d u a l b i t s a r e e q u a l

p o r t m a p ( i O = > a ( O ) , il=>b(O), eq=>eO);p o r t m a p ( i O = > a ( l ) , il=>b(i), eq=>el);

KI aeqb actual-signal,f rmal-s ignal => ctual-s ignal ,

) ;Th e first portion of the statement specifies which com pon ent is used. The u n i t - l a b e l termgives a unique id for an ins tance , the l i b n a m e term indicates wh ere (i.e., which library) thecomponent resides, and the e n t i t y n a m e an d archname terms indicate the nam es of the