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EMK310

Lecture 6

Introduction to PIC32

Prof. Tania Hanekom

References:PIC32MX3XX/4XX Family Data SheetPIC32 Family Reference ManualProgramming 32-bit Microcontrollers in C

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Device structure

PIC32MX architecture functional blocks: MCU Core System Memory

System Integration Peripherals

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Blockdiagram

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MCU core : MIPS architecture

32-bit RISC MIPS32 M4K Core MIPS (Microprocessor without Interlocked PipelineStages) RISC instruction set architecture developed by MIPS Computer

Systems

Pipelining CPUs built up from number of dedicated sub-units, e.g. instructiondecoders, ALUs (integer arithmetics and logic), load/store units(handling memory). Execution of instructions pass data from one tothe next.

Traditional non-optimized design:a particular instruction in a program

sequence must be (almost) completed before the next can be issuedfor execution

Pipelined architecture:successive instructions can overlap inexecution, eg., at the same time a math instruction is fed into the

floating point unit, the load/store unit can fetch the next instruction.

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MCU core : MIPS architecture (2)

Barrier to pipelining: some instructions (e.g. division) takelonger to complete; CPU has to wait before passing nextinstruction into pipeline.

One solution: series of interlocks that allows stages to indicate

that they are busy, pausing the other stages upstream. Interlocks: major performance barrier since they had to communicate

to all the modules in the CPU which takes time

MIPS design: fit every sub-phase, including cache-access, of allinstructions into one cycle, thereby removing any needs for

interlocking, and permitting a single cycle throughput.

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MCU core : MIPS architecture (3)

Other difference between MIPS & RISC: handling ofsubroutine calls

RISC: register windows hardware implementation limits the maximum depth of

multi-level calls Each subroutine call requires its own set of registers =

required more real estate on the CPU + more complexity indesign

MIPS: compiler find free registers for subroutines facilitated by increasing the number of registers

increases the performance of all tasks

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MCU core: ALU & Load-store

Single Cycle ALU

Load-Store Execution Unit

Load-store = values in memory must be brought

into the register file before they can be operated

upon

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MCU core: Pipeline

5-Stage Pipeline Instruction (I ) Stage

instruction is fetched

Execution (E) Stage Operands are fetched

ALU begins arithmetic orlogical operation

Memory (M) Stage ALU operation completes

data SRAM access performed

Align (A) Stage separate aligner aligns loaded

data with its word boundary

Writeback (W) Stage result is written back to the

register file

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MCU core: Buses & GPRs

32-bit Address and 32-bit Data Buses

Two 32-element, 32-bit General Purpose Register

Files

copy of the General Purpose Registers (GPR) for use by

high-priority interrupts = shadow register set

shadow set minimize context switching overhead during

interrupt/exception processing

used for integer operations and address calculation

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MCU core: FMT

FMT Fixed Mapping Translation Memory Management

FMT allows PIC32 to conform to programming model used by all otherMIPS-based designs so that standardized address spaces are used.

MIPS core: advanced features to allow separation of memory spacededicated to application(s) from that of operating system via use ofmemory management unit(MMU) and two distinct modes ofoperation: userand kernel.

MMU replaced by simplerfixed mapping translation (FMT) unit and abus matrix(BMX) control mechanism because embedded applicationsare less complex.

compatible scheme simplifies design of tools, applications and portingof code to PIC32

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MCU core: FMDU

FMDU Fast-Multiply-Divide Unit

PIC32 contains separate pipeline for multiply and divide

operations.

Pipeline operates in parallel with integer unit (IU) pipeline supports execution of one 16x16 or 32x16 multiply

operation every clock cycle; 32x32 multiply operations can

be issued every other clock cycle.

Divide operations implemented with 1 bit per clockiterative algorithm.

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MCU core: Instruction set

MIPS32 Compatible Instruction Set

MIPS16e Code Compression Instruction Set

Architecture Support

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System Memory

The PIC32 core offers some pretty advanced features

never before seen on 8- or 16-bit PIC architectures.

These include the ability to remap memory spaces,

to cache memory contents, and to share the memorybus with a direct memory access (DMA) mechanism.

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System memory: Virtual memory

PIC32MX microcontrollers implement two address spaces: virtual andphysical. All hardware resources, such as program memory, data memory and

peripherals, are located at their respective physical addresses.

Virtual addresses are exclusively used by the CPU to fetch and executeinstructions. (MIPS compatible)

Physical addresses are used by peripherals, such as DMA and Flash controllers,that access memory independently of the CPU.

4 GB unified virtual memory address space All memory regions, including program memory, data memory, SFRs and

configuration registers reside in this address space at their respective uniqueaddresses.

Program and data memories can be optionally partitioned into userand kernelmemories.

Data memory can be made executable, allowing the PIC32MX to execute fromdata memory.

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Virtual memory vs

Physical memory

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Flash Memory Technology

System memory provides on-chip nonvolatile Flashmemory and volatile SRAM memory

Flash

can be used for program memory or data. allows program memory to be electrically erased or

programmed under software control during normal deviceoperation.

has the capability to page erase, word or row program.

The PIC32MX series has full-speed execution directlyfrom program Flash through the use of on-chipprefetch buffering by the Prefetch module.

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System Integration

System integration consists of a comprehensive setof modules and features that tie the MCU core andperipheral modules into a single operational unit.

System integration features also provide theseadvantages:

Decreased system cost, by bringing traditionally off-chipfunctions into the microcontroller

Increased design flexibility, by adding a wider range of

operating modes

Increased system reliability, by enhancing the ability torecover from unexpected events

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System integration (continued)

The following sections of the PIC32 Family Reference Manual discuss thePIC32MX system integration: Section 3. Memory Organization

Section 4. Prefetch Module

Section 5. Flash Programming

Section 6. Oscillator

Section 7. Resets

Section 8. Interrupts

Section 9. Watchdog Timer and Power-up Timer

Section 10. Power-Saving Modes

Section 31. Direct Memory Access (DMA) Controller with programmable CyclicRedundancy Check (CRC)

Section 32. High-Level Integration (Configuration, Code Protection and VoltageRegulation)

Section 33. Device Programming, Debugging, In-Circuit and In-Circuit Testing

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Peripherals

P32RM Section 12. I/O Ports

P32RM Section 13. Parallel Master Port

P32RM Section 14. Timers

P32RM Section 15. Input Capture Module

P32RM Section 16. Output Compare/Pulse Width Modulation (PWM)

Module P32RM Section 17. 10-bit A/D Converter

P32RM Section 19. Comparator Module

P32RM Section 20. Comparator Voltage Reference Module

P32RM Section 21. UART Module

P32RM Section 23. SPI Module P32RM Section 24. I2C Module

P32RM Section 27. USB OTG

P32RM Section 29. Real-Time Clock/Calendar (RTCC) Module

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Device structure (recap)

PIC32MX architecture functional blocks: MCU Core System Memory

System Integration Peripherals

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Blockdiagramrevisited

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Coding lecture

Intro to MPLAB C32

Flashing an LED