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CS162Operating Systems andSystems Programming
Lecture 14
Caching andDemand Paging
October 14, 2009
Prof. John Kubiatowiczhttp://inst.eecs.berkeley.edu/~cs162
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Review: Memory Hierarchy of a Modern Computer System
Take advantage of the principle of locality to:
² Present as much memory as in the cheapest technology² Provide access at speed offered by the fastest technology
On- C
h i p
C a c h e
R e gi s t e r s
Control
Datapath
Secondary
Storage
(Disk)
Processor
Main
Memory
(DRAM)
Second
Level
Cache
(SRAM)
1s 10,000,000s(10s ms)
Speed (ns): 10s-100s 100s
100s GsSize (bytes): Ks-Ms Ms
Tertiary
Storage
(Tape)
10,000,000,000s(10s sec)
Ts
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Compulsory (cold start): first reference to a block
² ´Coldµ fact of life: not a whole lot you can do about it² Note: When running ´billionsµ of instruction, CompulsoryMisses are insignificant
Capacity:² Cache cannot contain all blocks access by the program
² Solution: increase cache size
Conflict (collision):² Multiple memory locations mapped to same cache location
² Solutions: increase cache size, or increase associativity
Two others:² Coherence (Invalidation): other process (e.g., I/O)updates memory
² Policy: Due to non-optimal replacement policy
Review: A Summary on Sources of Cache Misses
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Cache Index
0431
Cache TagByte Select
8
Cache Data
Cache Block 0
Cache TagValid
:: :
Cache Data
Cache Block 0
Cache Tag Valid
: ::
Mux 01Sel1 Sel0
OR
Hit
Review: Set Associative Cache
N-way set associative: N entries per Cache Index² N direct mapped caches operates in parallel
Example: Two-way set associative cache² Cache Index selects a ´setµ from the cache² Two tags in the set are compared to input in parallel² Data is selected based on the tag result
Compare Compare
Cache Block
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Example: Block 12 placed in 8 block cache
0 1 2 3 4 5 6 7Blockno.
Direct mapped:block 12 can go
only into block 4
(12 mod 8)
Set associative:block 12 can go
anywhere in set 0
(12 mod 4)
0 1 2 3 4 5 6 7Blockno.
Set
0
Set
1
Set
2
Set
3
Fully associative:block 12 can go
anywhere
0 1 2 3 4 5 6 7Blockno.
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
32-Block Address Space:
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3Block
no.
Review: Where does a Block Get Placed in a Cache?
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Goals for Today
Finish discussion of Caching/TLBs
Concept of Paging to Disk
Page Faults and TLB Faults
Precise Interrupts
Page Replacement Policies
Note: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and GagneNote: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne.Many slides generated from my lecture notes by Kubiatowicz.
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Easy for Direct Mapped: Only one possibility Set Associative or Fully Associative:
² Random
² LRU (Least Recently Used)
2-way 4-way 8-waySize LRU Random LRU Random LRU Random16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0%
64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5%
256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%
Which block should be replaced on a miss?
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Write through: The information is written to both the
block in the cache and to the block in the lower-levelmemory Write back: The information is written only to the
block in the cache.² Modified cache block is written to main memory onlywhen it is replaced
² Question is block clean or dirty? Pros and Cons of each?
² WT:» PRO: read misses cannot result in writes» CON: Processor held up on writes unless writes buffered
² WB:» PRO: repeated writes not sent to DRAM
processor not held up on writes» CON: More complex
Read miss may require writeback of dirty data
What happens on a write?
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Caching Applied to Address Translation
Question is one of page locality: does it exist?²
Instruction accesses spend a lot of time on the samepage (since accesses sequential)² Stack accesses have definite locality of reference² Data accesses have less page locality, but still some«
Can we have a TLB hierarchy?²
Sure: multiple levels at different sizes/speeds
Data Read or Write(untranslated)
CPU PhysicalMemory
TLB
Translate
(MMU)
No
VirtualAddress
Physical
Address YesCached?
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What Actually Happens on a TLB Miss?
Hardware traversed page tables:²
On TLB miss, hardware in MMU looks at current pagetable to fill TLB (may walk multiple levels)» If PTE valid, hardware fills TLB and processor never knows» If PTE marked as invalid, causes Page Fault, after which
kernel decides what to do afterwards
Software traversed Page tables (like MIPS)² On TLB miss, processor receives TLB fault² Kernel traverses page table to find PTE
» If PTE valid, fills TLB and returns from fault» If PTE marked as invalid, internally calls Page Fault handler
Most chip sets provide hardware traversal
² Modern operating systems tend to have more TLB faultssince they use translation for many things² Examples:
» shared segments» user-level portions of an operating system
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What happens on a Context Switch?
Need to do something, since TLBs map virtual
addresses to physical addresses² Address Space just changed, so TLB entries nolonger valid!
Options?² Invalidate TLB: simple but might be expensive
» What if switching frequently between processes?
² Include ProcessID in TLB» This is an architectural solution: needs hardware
What if translation tables change?
² For example, to move page from memory to disk orvice versa«
² Must invalidate TLB entry!» Otherwise, might think that page is still in memory!
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Administrative
Midterm I next week:²
Monday, 10/19, 6:00-9:00pm, 145 Dwinelle² Should be 2 hour exam with extra time² Closed book, one page of hand-written notes (both sides)
No class on day of Midterm² Extra Office Hours: Mon 2:00-5:00. Perhaps.
Midterm Topics² Topics: Everything up to Wednesday 10/14² History, Concurrency, Multithreading, Synchronization,Protection/Address Spaces, TLBs
Make sure to fill out Group Evaluations! Project 2
² Initial Design Document due tomorrow (Tuesday 10/13)² Look at the lecture schedule to keep up with due dates!
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What TLB organization makes sense?
Needs to be really fast² Critical path of memory access
» In simplest view: before the cache» Thus, this adds to access time (reducing cache speed)
² Seems to argue for Direct Mapped or Low Associativity However, needs to have very few conflicts!
² With TLB, the Miss Time extremely high!² This argues that cost of Conflict (Miss Time) is muchhigher than slightly increased cost of access (Hit Time)
Thrashing: continuous conflicts between accesses² What if use low order bits of page as index into TLB?
» First page of code, data, stack may map to same entry» Need 3-way associativity at least?
² What if use high order bits as index?»
TLB mostly unused for small programs
CPU TLB Cache Memory
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TLB organization: include protection
How big does TLB actually have to be?² Usually small: 128-512 entries² Not very big, can support higher associativity
TLB usually organized as fully-associative cache² Lookup is by Virtual Address² Returns Physical Address + other info
Example for MIPS R3000:
What happens when fully-associative is too slow?² Put a small (4-16 entry) direct-mapped cache in front² Called a ´TLB Sliceµ
When does TLB lookup occur?² Before cache lookup?² In parallel with cache lookup?
0xFA00 0x0003 Y N Y R/W 34
0x0040 0x0010 N Y Y R 0
0x0041 0x0011 N Y Y R 0
Virtual Address Physical Address Dirty Ref Valid Access ASID
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Example: R3000 pipeline includes TLB ´stagesµ
Inst Fetch Dcd/ Reg ALU / E.A Memory Write Reg
TLB I-Cache RF Operation WB
E.A. TLB D-Cache
MIPS R3000 Pipeline
ASID V. Page Number Offset
12206
0xx User segment (caching based on PT/TLB entry)
100 Kernel physical space, cached
101 Kernel physical space, uncached
11x Kernel virtual space
Allows context switching among
64 user processes without TLB flush
Virtual Address Space
TLB
64 entry, on-chip, fully associative, software TLB fault handler
CombinationSegments and
Paging!
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As described, TLB lookup is in serial with cache lookup:
Machines with TLBs go one step further: they overlapTLB lookup with cache access.² Works because offset available early
Reducing translation time further
Virtual Address
TLB Lookup
VAccessRights PA
V page no. offset10
P page no. offset
10
Physical Address
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Here is how this might work with a 4K cache:
What if cache size is increased to 8KB?
² Overlap not complete² Need to do something else. See CS152/252
Another option: Virtual Caches² Tags in cache are virtual addresses² Translation only happens on cache misses
TLB 4K Cache
10 2
004 bytes
index 1 K
page # disp20
assoclookup
32
Hit/Miss
FN Data Hit/Miss
=FN
Overlapping TLB & Cache Access
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Demand Paging
Modern programs require a lot of physical memory²
Memory per system growing faster than 25%-30%/year But they don·t use all their memory all of the time
² 90-10 rule: programs spend 90% of their time in 10%of their code
² Wasteful to require all of user·s code to be in memory
Solution: use main memory as cache for disk
On- Ch i p
C a c h e
Control
Datapath
SecondaryStorage
(Disk)
Processor
MainMemory
(DRAM)
SecondLevel
Cache
(SRAM)
Tertiary
Storage(Tape)
Caching
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PageTable
T L B
Illusion of Infinite Memory
Disk is larger than physical memory ² In-use virtual memory can be bigger than physical memory² Combined memory of running processes much larger thanphysical memory» More programs fit into memory, allowing more concurrency
Principle: Transparent Level of Indirection (page table)² Supports flexible placement of physical data
» Data could be on disk or somewhere across network² Variable location of data transparent to user program
» Performance issue, not correctness issue
PhysicalMemory512 MB
Disk500GB
g
VirtualMemory4 GB
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Demand Paging is Caching
Since Demand Paging is Caching, must ask:
² What is block size?» 1 page
² What is organization of this cache (i.e. direct-mapped,set-associative, fully-associative)?» Fully associative: arbitrary virtualpphysical mapping
² How do we find a page in the cache when look for it?» First check TLB, then page-table traversal
² What is page replacement policy? (i.e. LRU, Random«)» This requires more explanation« (kinda LRU)
² What happens on a miss?» Go to lower level to fill miss (i.e. disk)
² What happens on a write? (write-through, write back)» Definitely write-back. Need dirty bit!
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Review: What is in a PTE?
What is in a Page Table Entry (or PTE)?² Pointer to next-level page table or to actual page² Permission bits: valid, read-only, read-write, write-only
Example: Intel x86 architecture PTE:² Address same format previous slide (10, 10, 12-bit offset)² Intermediate page tables called ´Directoriesµ
P: Present (same as ´validµ bit in other architectures)W: WriteableU: User accessible
PWT: Page write transparent: external cache write-throughPCD: Page cache disabled (page cannot be cached)A: Accessed: page has been accessed recentlyD: Dirty (PTE only): page has been modified recentlyL: L=14MB page (directory only).
Bottom 22 bits of virtual address serve as offset
Page Frame Number
(Physical Page Number)
Free
(OS) 0 L D A
P
C D
P W T
U W P01234567811-931-12
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PTE helps us implement demand paging² Valid Page in memory, PTE points at physical page² Not Valid Page not in memory; use info in PTE to findit on disk when necessary
Suppose user references page with invalid PTE?² Memory Management Unit (MMU) traps to OS
» Resulting trap is a ´Page Faultµ
² What does OS do on a Page Fault?:» Choose an old page to replace» If old page modified (´D=1µ), write contents back to disk» Change its PTE and any cached TLB to be invalid» Load new page into memory from disk»
Update page table entry, invalidate TLB for new entry» Continue thread from original faulting location² TLB for new page will be loaded when thread continued!² While pulling pages off disk for one process, OS runsanother process from ready queue» Suspended process sits on wait queue
Demand Paging Mechanisms
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Software-Loaded TLB
MIPS/Nachos TLB is loaded by software² High TLB hit rateok to trap to software to fill the
TLB, even if slower² Simpler hardware and added flexibility: software canmaintain translation tables in whatever convenient format
How can a process run without access to page table?² Fast path (TLB hit with valid=1):
» Translation to physical page done by hardware² Slow path (TLB hit with valid=0 or TLB miss)
» Hardware receives a ´TLB Faultµ² What does OS do on a TLB Fault?
» Traverse page table to find appropriate PTE»
If valid=1, load page table entry into TLB, continue thread» If valid=0, perform ´Page Faultµ detailed previously» Continue thread
Everything is transparent to the user process:² It doesn·t know about paging to/from disk² It doesn·t even know about software TLB handling
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Transparent Exceptions
How to transparently restart faulting instructions?² Could we just skip it?
» No: need to perform load or store after reconnectingphysical page
Hardware must help out by saving:²
Faulting instruction and partial state» Need to know which instruction caused fault» Is single PC sufficient to identify faulting position????
² Processor State: sufficient to restart user thread» Save/restore registers, stack, etc
What if an instruction has side-effects?
Load TLB
F a
u l t i n g
I n
s t
1
F a u l t i n g
I n
s t
1
F a u l t i n g
I n
s t
2
F a u l t i n g
I n
s t
2
Fetch page/Load TLB
User
OS
TLB Faults
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Consider weird things that can happen What if an instruction has side effects?
² Options:»
Unwind side-effects (easy to restart)» Finish off side-effects (messy!)
² Example 1: mov (sp)+,10» What if page fault occurs when write to stack pointer?» Did sp get incremented before or after the page fault?
² Example 2: strcpy (r1), (r2)
» Source and destination overlap: can·t unwind in principle!» IBM S/370 and VAX solution: execute twice ² once
read-only What about ´RISCµ processors?
² For instance delayed branches?» Example: bne som ewhere
ld r1,(sp)» Precise exception state consists of two PCs: PC and nPC
² Delayed exceptions:» Example: div r1, r2, r3
ld r1, (sp)
» What if takes many cycles to discover divide by zero,
but load has already caused page fault?
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Precise Exceptions
Precise state of the machine is preserved as ifprogram executed up to the offending instruction² All previous instructions completed² Offending instruction and all following instructions act asif they have not even started
² Same system code will work on different implementations² Difficult in the presence of pipelining, out-of-order
execution, ...² MIPS takes this position
Imprecise system software has to figure out what iswhere and put it all back together
Performance goals often lead designers to forsake
precise interrupts² system software developers, user, markets etc. usuallywish they had not done this
Modern techniques for out-of-order execution andbranch prediction help implement precise interrupts
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Page Replacement Policies
Why do we care about Replacement Policy?² Replacement is an issue with any cache² Particularly important with pages
» The cost of being wrong is high: must go to disk» Must keep important pages in memory, not toss them out
What about MIN?² Replace page that won·t be used for the longest time² Great, but can·t really know future«² Makes good comparison case, however
What about RANDOM?² Pick random page for every replacement² Typical solution for TLB·s. Simple hardware² Pretty unpredictable ² makes it hard to make real-time
guarantees What about FIFO?
² Throw out oldest page. Be fair ² let every page live inmemory for same amount of time.
² Bad, because throws out heavily used pages instead ofinfrequently used pages
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Replacement Policies (Con·t)
What about LRU?² Replace page that hasn·t been used for the longest time² Programs have locality, so if something not used for awhile, unlikely to be used in the near future.
² Seems like LRU should be a good approximation to MIN. How to implement LRU? Use a list!
² On each use, remove page from list and place at head² LRU page is at tail
Problems with this scheme for paging?² Need to know immediately when each page used so thatcan change position in list«
² Many instructions for each hardware access In practice, people approximate LRU (more later)
Page 6 Page 7 Page 1 Page 2Head
Tail (LRU)
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Summary
TLB is cache on translations² Fully associative to reduce conflicts² Can be overlapped with cache access
Demand Paging:² Treat memory as cache on disk² Cache miss get page from disk
Transparent Level of Indirection² User program is unaware of activities of OS behind scenes² Data can be moved without affecting application correctness
Software-loaded TLB² Fast Path: handled in hardware (TLB hit with valid=1)² Slow Path: Trap to software to scan page table
Precise Exception specifies a single instruction for which:²
All previous instructions have completed (committed state)² No following instructions nor actual instruction have started Replacement policies
² FIFO: Place pages on queue, replace page at end² MIN: replace page that will be used farthest in future² LRU: Replace page that hasn·t be used for the longest time